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Call for Paper
Call for papers
Important Dates:
✓ Final Deadline for Full Paper Submission:July 31, 2022 extended till August 10, 2022
✓ Notification for Acceptance:
Sept 30, 2022
✓ Conference:
08-12 January 2023 @ Novotel, HICC, Hyderabad
✓ Final Deadline for Full Paper Submission: July 31, 2022 extended till August 10, 2022
✓ Notification for Acceptance: Sept 30, 2022
✓ Conference: 08-12 January 2023 @ Novotel, HICC, Hyderabad
CFP Topics
cfp topics
Hardware for AI and ML:
Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence, AI accelerator design, AI boosted circuits and systems for Brain Machine Interface, Memory Centric Accelerator Design, Low power autonomous systems.
Embedded Systems Design:
ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems, Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip, Embedded for automotive and Electric Vehicles
Analog & Mixed Signal circuits:
Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces.
Low power Digital Architectures:
Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.
Photonic Integrated Circuits:
Silicon and III-V Photonic Integrated Circuits, Waveguides/interconnects, On-chip lasers, Optical Multiplexers/Demultiplexers, Photo detectors and sensors, Quantum photonics, RF Photonics, Mid-IR/THz Photonics, Heterogeneous integration, Packaging of Photonic devices, Quantum photonics, RF Photonics, Mid-IR and THz Photonics.
Advances in CAD for VLSI:
Logic and behavioural synthesis, logic mapping, simulation and formal verification, physical design techniques, post route optimizations, simulation Tools for Design Verification, Static Timing and Timing Exceptions, Mixed Signal Simulations in sub 10 nm nodes.
RF Circuits and Wireless systems:
RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging. Reliability aspects in RFICs.
Latest trends in device design and modelling:
Deep nanoscale CMOS devices, device modeling and simulation, multi-domain simulation, device/circuit-level reliability and variability, Devices for beyond CMOS, compact modeling and novel TCAD solutions.
Wireline and Optical Communication Circuits and Systems:
Receivers/transmitters/transceivers for wireline systems, exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation and distribution circuits including PLLs, line drivers, and hybrids).
Beyond 2D in Packaging and interconnects:
Wafer-level packaging, embedded chip packaging, 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation, component, system and product level thermal management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects.
Sensors interfacing circuits and systems:
Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits and systems for IoT.
Power and Energy Management:
Power management and control circuits, regulators; power converter ICs, energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators, Power management for automotive systems, battery management circuits and systems.
Neuromorphic Circuits and Systems:
Device, circuit, architecture design, analysis and optimization for neuromorphic computing systems, Complexity and scalability of neuromorphic computing, Emerging technologies for brain-inspired nano-computing and communication, Applications of neuromorphic computing in embedded and IoT devices, unmanned vehicles and drones, and cyber-physical systems.
Test and Reliability:
Simulation, formal verification, validation at different abstraction levels, DFT, fault modelling and simulation, ATPG, BIST, fault tolerance, post-silicon validation and debug, delay test, memory test, reliability testing.
Please Note:
All papers must be in PDF format only, with save-able text.
- Each paper must be no more than 6 pages (including the abstract, figures, tables, and references), double-columned in IEEE Format
- Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person.
- Submissions not adhering to these rules, or determined to be previously published or simultaneously submitted to another conference, or journal, will be summarily rejected.
- The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules.
For questions Contact: [email protected]
