Global Synergy in Silicon: VLSI and Embedded AI for Sustainable Computing and Next-Gen Electrified Mobility
Registration
Collect your Badges at the Registration Desk.
Time: 8.00 AM to 9.00 AM
Tutorial Chair : Dr. John Jose
9.30 AM to 11.00 AM
Title - Supercharge your RISC-V Designs with Higher Abstraction Shift-Left
Speaker : Ayush Mewati & Aditya Tiwari - CircuitSutra Technologies
Session Chair : Sivanantham S - VIT Vellore
Session Chair : Sivanantham S - VIT Vellore
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
Safe and Secure RISC-V Processors for Software-Defined-Vehicles
Sourav Roy & Neha Srivastava - NXP
Session Chair : Amlan Chakrabarti - University of Calcutta
Session Chair : Amlan Chakrabarti - University of Calcutta
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Foundry Compliance and Tapeout Readiness - A Complete Framework from Design Verification to Silicon Qualification
Venkata Reddy Kolagatla & Vivian Desalphine - CDAC
Session Chair : Amlan Chakrabarti - University of Calcutta
Session Chair : Amlan Chakrabarti - University of Calcutta
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
Physical Design and Timing Closure challenges in advance technology nodes
Vinayak Mehetre - Qualcomm
Session Chair : Satyajit Das - IIT Guwahati
Session Chair : Satyajit Das - IIT Guwahati
Track Chair: Dr. Sumantra Sarkar
9.30 AM to 11.00 AM
Brains and Brawn: AI for Hardware, Hardware for AI
Sri Parameswaran - UNSW Syndney, Siddharth Garg - NYU Tandon, Soumya J & Paresh Saxena - BITS Pilani - Hyderbad
Session Chair : Manojit Ghose - IIT Guwahati
Session Chair : Manojit Ghose - IIT Guwahati
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.00 AM to 01.00 PM
CONTINUED - Brains and Brawn: AI for Hardware, Hardware for AI
Sri Parameswaran - UNSW Syndney, Siddharth Garg - NYU Tandon, Soumya J & Paresh Saxena - BITS Pilani - Hyderbad
Session Chair : Manojit Ghose - IIT Guwahati
Session Chair : Manojit Ghose - IIT Guwahati
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
ADAS & Autonomous Driving – Hardware & Software System
Vivek Vasantha - Renesas India
Session Chair : Navneet Kaur - Chandigarh University
Session Chair : Navneet Kaur - Chandigarh University
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
Automotive Functional Safety for Semiconductor
Prasanna Venkatesh B - HCL Tech
Session Chair : Sangmeshwar Kendre - BITS
Session Chair : Sangmeshwar Kendre - BITS
Track Chair: Mr. Biswadeep Chatterjee
9.30 AM to 11.00 AM
Reliability at Scale in Enterprise Hardware
Anand Venkitasubramani & Daniel Lewis - IBM
Session Chair : Shivani Pandita - BITS
Session Chair : Shivani Pandita - BITS
11 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
Low-Power High-Performance architectures for High-Speed Pipeline ADCs
Nithin Gopinath - Texas Instruments
Session Chair : Sanjeet Kumar Sinha - LPU
Session Chair : Sanjeet Kumar Sinha - LPU
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
FPGA-Based System Design for VLSI Engineers: Leveraging Lattice Solution
Prashant Deokar & Vishal Sonawane - Lattice Semiconductor
Session Chair : Shylashree N - RVCE
Session Chair : Shylashree N - RVCE
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
High Bandwidth Memory: Memory For AI
Ramesh Natesh, Narayana Reddy Yatam & Shashikumar Gautam - Micron
Session Chair : Phrangboklang L. Thangkhiew - IIT Guwahati
Session Chair : Phrangboklang L. Thangkhiew - IIT Guwahati
Track Chair: Dr Mansi Subhedar
9.30 AM to 11.00 AM
Decoding Raw Echoes for Space based Earth Intelligence: SAR and Optical Processing with Edge Computing
Denil Chawda - GalaxEye
Session Chair : Mahesh Kumawat - Bennett University
Session Chair : Mahesh Kumawat - Bennett University
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
Micro-architecture Modeling for Application Specific Neural Network on Digital Semiconductor Device
Amol Bharat Ranadive - Esicompute
Session Chair : Saravanan P - PSG Tech
Session Chair : Saravanan P - PSG Tech
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Time Sensitive Networking and its Application in Software Defined Vehicles: Protocols, Scheduling and Performance Guarantees
Arnab Sarkar - IIT KGP, Arijit Mondal - IITP & Jaishree Mayank - IIT-ISMD
Session Chair : T. Venkatesh - IIT Guwahati
Session Chair : T. Venkatesh - IIT Guwahati
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
CONTINUED : Time Sensitive Networking and its Application in Software Defined Vehicles: Protocols, Scheduling and Performance Guarantees
Arnab Sarkar - IIT KGP, Arijit Mondal - IITP & Jaishree Mayank - IIT-ISMD
Session Chair : T. Venkatesh - IIT Guwahati
Session Chair : T. Venkatesh - IIT Guwahati
9.00 AM to 09.30 AM - Keynote : Manish Karle, Deputy Director, Technology Group, ARAI
Track Chair: Dr. John Jose
9.30 AM to 11.00 AM
Energy-Efficient Acceleration with Coarse-Grained Reconfigurable Arrays: From Fundamentals to Applications
Satyajit Das - IIT Guwahati, Chilankamol Sunny - AMD
Session Chair : Dinesha P - DSCE Bengaluru
Session Chair : Dinesha P - DSCE Bengaluru
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
CONTINUED : Energy-Efficient Acceleration with Coarse-Grained Reconfigurable Arrays: From Fundamentals to Applications
Satyajit Das - IIT Guwahati, Chilankamol Sunny - AMD
Session Chair : Dinesha P - DSCE Bengaluru
Session Chair : Dinesha P - DSCE Bengaluru
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Scalable System Simulation for Large Language Model Workloads
Debjyoti Bhattacharjee & Arindam Mallik - IMEC
Session Chair : Sonal Yadav - NIT Raipur
Session Chair : Sonal Yadav - NIT Raipur
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
CONTINUED : Scalable System Simulation for Large Language Model Workloads
Debjyoti Bhattacharjee & Arindam Mallik - IMEC
Session Chair : Sonal Yadav - NIT Raipur
Session Chair : Sonal Yadav - NIT Raipur
Track Chair: Dr. Sumantra Sarkar
9.30 AM to 11.00 AM
Chip Design Simplified using Agentic AI
Arpan Sircar & Shivsantosh Singh - Intel
Session Chair : Biswadeep Chatterjee - HCL
Session Chair : Biswadeep Chatterjee - HCL
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 01.00 PM
Clock Domain Crossing and Synchronization
Sanjay Churiwala - AMD
Session Chair : Varun Sharma - Real Intent
Session Chair : Varun Sharma - Real Intent
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
EDA Routing and Technology Enablement at Advanced Nodes
Diwesh Pandey & Mithula Madiraju - IBM
Session Chair : Sumantra Sarkar - AMD
Session Chair : Sumantra Sarkar - AMD
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
Introduction to quantum computing and Engineering Scalable Quantum Systems: The Role of Superconducting Circuits
Dr. Anindita Banerjee - C-DAC, Pepijn Kluytmans - Quantware & Siddharth Kalra - Quantware
Session Chair : Ruchika Gupta - Chandigarh University
Session Chair : Ruchika Gupta - Chandigarh University
Track Chair: Mr. Biswadeep Chatterjee
9.30 AM to 11.00 AM
Achieving Energy Efficiency in AI/ML and HPC Hardware: A Case for Hardware/Software Co-Design?
Tovinakere Dwarakanath Vivek & Deeksha C. Goplani - AMD
Session Chair : Mansi Subhedar - PHCET Navi Mumbai
Session Chair : Mansi Subhedar - PHCET Navi Mumbai
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
Energy Proportional Rapid-On/Off Serial Links for Data Centers
Saurabh Saxena - IIT Madras
Session Chair : Mansi Subhedar - PHCET Navi Mumbai
Session Chair : Mansi Subhedar - PHCET Navi Mumbai
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Neuromorphic Horizons: Spiking Neural Networks for Ultra-Low-Power AI at the Sensor Edge
Alex P. James - DUK, George Vathakkattil Joseph & Aditya Dalakoti - Innatera Nanosystems, Luke Theogarajan UCSB
Session Chair : Anand Darji - SVNIT Surat
Session Chair : Anand Darji - SVNIT Surat
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
CONTINUED - Neuromorphic Horizons: Spiking Neural Networks for Ultra-Low-Power AI at the Sensor Edge
Alex P. James - DUK, George Vathakkattil Joseph & Aditya Dalakoti - Innatera Nanosystems, Luke Theogarajan UCSB
Session Chair : Satyajit Das - IIT Guwahati
Session Chair : Satyajit Das - IIT Guwahati
Track Chair: Dr Mansi Subhedar
9.30 AM to 11.00 AM
Post-CMOS Computing Architectures
Vijaykrishnan Narayanan - Penn State, Ahmedullah Aziz UTK & Nikhil Shukla UVA
Session Chair : T.V. Kalyan - IIT Ropar
Session Chair : T.V. Kalyan - IIT Ropar
11.00 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
CONTINUED : Post-CMOS Computing Architectures
Vijaykrishnan Narayanan - Penn State, Ahmedullah Aziz UTK & Nikhil Shukla UVA
Session Chair : T.V. Kalyan - IIT Ropar
Session Chair : T.V. Kalyan - IIT Ropar
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Carbon-conscious AI Acceleration with Silicon Photonics: From Device Modeling to System Simulation
Dharanidhar Dang - UTSA, Ahmedullah Aziz - UTK & Priyabrata Dash - UTSA
Session Chair : K N Vijeyakumar - SECE
Session Chair : K N Vijeyakumar - SECE
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
Drone Design: The Practical Approach
Pranav Virmani - Botlab Technologies
Session Chair : Ayoob Khan T E - CEC
Session Chair : Ayoob Khan T E - CEC
Registration - 7:30 AM to 9:00 A.M.
9.00 AM to 10.00 AM
Inaugural
Shri Devendra Fadnavis - Hon`ble Chief Minister of Maharashtra
In presence of
Shri Shivendra Raje Bhosale - Minister of Public Works, Govt of Maharashtra
Shri Uday Samant - Minister for Industries, Govt of Maharashtra
Mr. Rajendra Chodankar - CEO and Chairman, RRP Group
Dr. Satya Gupta - President, VLSI Society of India
Mr. Vinayak Godse - CEO, DSCI
Mr. Pravin Desale - SVP, Lattice Semiconductor
Dr. Ashish Darbari - Founder & CEO, Axiomise
Dr. Rahul Karad - Managing Trustee & Executive President, MITWPU Pune
Mr. Shailesh Parab - Country Manager, Sales, SEMTECH, India
In presence of
Shri Shivendra Raje Bhosale - Minister of Public Works, Govt of Maharashtra
Shri Uday Samant - Minister for Industries, Govt of Maharashtra
Mr. Rajendra Chodankar - CEO and Chairman, RRP Group
Dr. Satya Gupta - President, VLSI Society of India
Mr. Vinayak Godse - CEO, DSCI
Mr. Pravin Desale - SVP, Lattice Semiconductor
Dr. Ashish Darbari - Founder & CEO, Axiomise
Dr. Rahul Karad - Managing Trustee & Executive President, MITWPU Pune
Mr. Shailesh Parab - Country Manager, Sales, SEMTECH, India
10.00 AM to 10.30 AM
Vision Address - Closing the Silicon Loop: India’s Journey from Wafer Fabrication to Finished Chips
Rajendra Chodankar - CEO, RRP Group of Companies
10.30 AM to 11.00 AM
Keynote Address - Powering the Future – How Low Power FPGAs are Shaping Tomorrows Tech Landscape
Pravin Desale - SVP, Lattice Semiconductor
11.00 AM to 11.20 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.20 AM to 11.50 AM
Vision Address -2
Prem Natarajan - EVP & Chief Scientist, Capital One
11.50 AM to 12.20 PM
Keynote Address - Formal verification - Breaking adoption barriers by scaling deployment on billion-gate designs
Dr. Ashish Darbari - Founder & CEO, Axiomise
12.20 AM to 12.40 PM
Keynote Address (KD1-3)
Prof. Subhasish Mitra - William E. Ayer Endowed Chair Professor, Stanford
12.40 PM to 01.05 PM
Engineering in the Age of AI: Musings Across Time and Technology
Sumedha Limaye - VP, Quest Global
01.05 PM to 2.05 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.05 PM to 2.30 PM
Keynote-P-2
Michel Sarlotte - Chef de service chez, Thales
2.30 PM to 2.50 PM
Keynote Address - Challenges and Opportunities for semiconductor in AI era
Gokul V Subramaniam - President & VP, Intel India
2.50 PM to 3.10 PM
Keynote Address (KD1-7)
Dr. P. Anbalagan IAS - Government of Maharashtra
3.10 PM to 3.30 PM
Keynote Address (KD1-8)
Sumit Goswami - VP, Qualcomm
3.30 PM to 4.00 PM
Fireside Chat - (FD1-1) SWAPN (Swadeshi Product Nation)
Dr. Satya Gupta, Sanjay Nayak, Jaswinder Ahuja
4.00 PM to 4.20 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
04.20 PM to 06.00 PM - Breakout sessions in Rooms .. Sabha 1, Sabha 2, Sabha 3, BRM 1, BRM 2, BRM 3, BRM 4 & BRM 5
6.00 PM to 6.30 PM
BREAK
06.30 PM to 07.30 PM - SwadeSilicon Workshop
4.20 PM to 04.40 PM
A current injection based Constant-gm Rail to Rail OTA Achieving Uniform Small- and Large-Signal Behaviour by
Mohammed Hammad Khan & Abhishek Srivastava
04.40 PM to 05.00 PM
A Robust CMOS Schmitt Trigger Architecture with Improved Noise Immunity and Hysteresis Control by
Siddharth R. K., Shasidhar Reddy, Deepankar Cheni, Karteek Dokala, Nithin Kumar Y.B. & Vasantha M.H.
05.00 PM to 05.20 PM
A 3nm Silicon proven mechanism to eliminate ground bounce impact for high-precision analog HVM trim in digital processors by
Anup Deka, Balabrahmachari Matcha, Sanjay Singh & Subbu Manam
05.20 PM to 05.40 PM
A Partially Loop-Unrolled Noise-Shaping SAR ADC achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology by
Anamika Sharma, Luv Pandey, Paras Garg and Rajesh Zele
05.40 PM to 06.00 PM
A Low Power 8-bit 3GS/s Current Steering DAC at 1.2V supply achieving > 49dB SFDR in 65nm CMOS by
Anamika Sharma & Rajesh Zele
4.20 PM to 04.40 PM
Invited talk by
Jaydeep Kulkarni
04.40 PM to 05.00 PM
Energy Efficient Spiking Neural Networks for Temporal Patterns Using EvoSNN-MO by
Murali Krishna Yadav, B Naresh Kumar Reddy, Y Charan Krishna & Talluri Vineel Jessy
05.00 PM to 05.20 PM
XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads by
Tejas Chaudhari, Akarsh J, Tanushree Dewangan, Mukul Lokhande & Santosh Vishvakarma
05.20 PM to 05.40 PM
A 98.5-TOPS/W and 0.73-TOPS/mm^2 Digital Compute-In-Memory Macro with a Novel 6T+MUX Bitcell For Sparsity-Aware MAC Operations by
Priyanshu Tyagi, Aayush Gautam and Sparsh Mittal
05.40 PM to 06.00 PM
Energy and Performance Optimized Computation Offloading for Near-Memory Computing by
Apratim Goswami, Satanu Maity & Manojit Ghose
4.20 PM to 04.40 PM
PolyEMAC: Polynomial Error Metrics Analysis in Approximate Computing
Mohamed Nadeem, Chandan Kumar Jha & Rolf Drechsler
04.40 PM to 05.00 PM
PIDArc: Physics-Informed DeMuxed Architecture for Enhanced Aging-Aware Leakage Power Estimation for FinFET Logic Cells by
Mohammad Rehan Akhtar & Zia Abbas
05.00 PM to 05.20 PM
AAMLA: An Autonomous Agentic Framework for Memory-Aware LLM-Aided Hardware Generation by
Rajat Bhattacharjya, Juhee Sung, Hangyeol Jung, Hyunwoo Oh, Arnab Sarkar, Mohsen Imani & Nikil Dutt
05.20 PM to 05.40 PM
Leveraging XAI for Semiconductor Electrical – Parameter Characterization using Machine Learning by
Siddhi Srivastava, Debojyoti Roy, Hriddhi Srivastava, Khushwant Sehra and Manoj Saxena
05.40 PM to 06.00 PM
Invited talk by
Akash Kumar
4.20 PM to 04.40 PM
A Fully Reconfigurable and Adaptable Current-Source based Sense Amplifier for Energy Efficient In-Memory Computing by
Parminder Kaur, Sai Laxman Charagundla & Amandeep Kaur
04.40 PM to 05.00 PM
PowerShift: Leveraging Power-Aware Weight Approximations for Neural Network Acceleration by
Vishesh Mishra, Sparsh Mittal & Urbi Chatterjee
05.00 PM to 05.20 PM
FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic Packing by
Suprabhat Bhattacharjee & Ayan Palchaudhuri
05.20 PM to 05.40 PM
RAMFORM: A Ramanujan Wavelet Transform-based Accelerator for Energy-efficient Signal Processing by
Arya Pandit, Soham Das, Arghadip Das, Debaprasad De, Arnab Raha and Mrinal Kanti Naskar
05.40 PM to 06.00 PM
NIR-DST: Noise-Immune Radiation Hardened Dual-Modal Domino-Schmitt Architecture by
Govind Prasad, Het Patel, Lakshya Singhal, Sai Ankit Sahoo & Anmol Aggarwal
Design Contest
4.20 PM to 06.00 PM
Platform 1: Lattice Semiconductors CPNX VVML FPGA:
1. FPGA-Based CNN Accelerator Integrated with RISC-V SoC for Silicon Wafer Defect Classification
by Priyanshu Tyagi & Sparsh Mittal (IIT Roorkee), Rhythm Patel (SVNIT Surat)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
Platform 2: Microchip Technologys PolarFire SoC Icicle Kit:
1. TRINETRA: Seeing Beyond Vision
by Akshat Sharma, Tanvi R, Dr. Chethana G (RV College of Engineering)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
Platform 3: Qubit Designing using Qiskit Metal:
1. Readout-Optimized Transmon Qubit as a Quantum Front-End for VLSI Decoding Accelerators.
by Aman Raj Saurav, Priyam Mishra, Tushar Garg, Satyam Chauhan, Prof Jawar Singh (Indian Institute of Technology Patna)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
4.20 PM to 04.40 PM
Moschip - ASICs to Agentic AI - Powering the Next Wave of Intelligent Systems! by
Vishal Patil - Senior Vice President - Product Engineering BU, MosChip Technologies
04.40 PM to 05.00 PM
Renesas - Compute Memory wall - opportunities and challenges in AI world by
Ananda Sitaraman - Director, Memory Interface Division
05.00 PM to 05.20 PM
BITS Pilani - "Co-Creating Future-Ready Talent through Industry–Academia Collaboration and Work-Integrated Learning" by
Dr. Prakruthi Hareesh
05.20 PM to 05.40 PM
STMicroelctronics - Edge Computing (AI) Solutions by
Manuj Ayodhyawasi - Senior Principal Engineer, Embedded AI Solutions
05.40 PM to 06.00 PM
SigaSi - Safe and Seamless Integration of AI into RTL design with Sigasi Visual HDL by
Daniel Geel - Account Executive
06.00 PM to 06.20 PM
Einfochips - Advanced Automotive Architecture- Zone Controller- A journey and insights from Silicon solution by
Mangesh Kulkarni - VP & GM [ASIC], eInfochips
Tape-out Contest
4.20 PM to 04.40 PM
A Configurable Time-Domain In-Memory Computing Macro for Multi-Bit MAC and Binary XAC Operations in Edge AI Devices
04.40 PM to 05.00 PM
ASIC Implementation of Convolutional Layer of CNN
05.00 PM to 05.20 PM
Design of Encrypted 8b/10b Serializer and De-Serializer (SerDes)
05.20 PM to 05.40 PM
Precision Farming
05.40 PM to 06.00 PM
Design and fabrication of fully digital Modem and FIFO buffer for Indian long range (i-LoRa) application for the consortium project entitled ML enabled RISC-V based i-LoRa SOC for forest event monitoring
Registration - 8:00 AM to 9:00 A.M.
09.00 AM to 09.20 AM
Keynote Address (KD2-1)
Srikanth Settikere - VP and MD, Microchip
09.20 AM to 09.50 AM
Vision Address (VD2-1)
Vamsi Boppana - SVP of AI, AMD
09.50 AM to 10.10 AM
Keynote Address - Shaping the next generation of VLSI design with AI-powered innovation
Ankur Gupta - Executive Vice President, Siemens Digital Industries Software
10.10AM to 10.30 AM
Keynote Address (KD2-3)
Boyd Phelps - SVP, Cadence
10.30 AM to 10.50 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
10.50 AM to 11.10 AM
Keynote Address - Systems Engineering in the Silicon to Systems Era
Jayraj Nair - Field CTO, Synopsys
11.10 AM to 11.30 AM
Keynote Address - Intelligence at the Edge -Driving the Autonomous World Forward
Hitesh Garg - VP & India Country Manager, NXP
11.30 AM to 11.50 AM
Keynote Address (KD2-6)
Prof. Udayan Ganguly - IIT Bombay
11.50 AM to 12.10 PM
Keynote Address (KD2-7)
Ravi Shankar R - CEO, Proxelera
12.10 AM to 12.30 PM
Keynote Address - AI Driven Design in the Zettabyte Era - What’s Real Today and What’s Next ?
Prasad Sandireddy - VP, Sandisk
12.30 AM to 01.15 PM
Panel Discussion - "NexGen Semiconductor Innovations for AI Enabled Systems": by
Moshiko Emmer - Distinguished Engineer, Cadence Design Systems
Sharat Babu - Director of Systems Design Engineering, Adaptive and Embedded Computing Group (AECG), AMD
Ruchir Dixit - VP and Country Manager , Siemens EDA
Eleena Ong - CVP, Software Systems & Application Engineering, Lattice Semiconductors
Dr. Subhrakanti Das - Head of Department, Research Technology and Innovation, Thales
Sumit Goswami - VP Engineering, Qualcomm (Moderator)
Sharat Babu - Director of Systems Design Engineering, Adaptive and Embedded Computing Group (AECG), AMD
Ruchir Dixit - VP and Country Manager , Siemens EDA
Eleena Ong - CVP, Software Systems & Application Engineering, Lattice Semiconductors
Dr. Subhrakanti Das - Head of Department, Research Technology and Innovation, Thales
Sumit Goswami - VP Engineering, Qualcomm (Moderator)
01.15 PM to 2.10 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.10 PM to 2.55 PM
Panel Disussion - Swadeshi to Silicon, Advancing India`s Product-Led Semiconductor Future
Apoorva Raut - CTO, RRP Electronics Limited
Swamy Irrinki - EVP, Worldwide Sales & Marketing, MosChip
Prasad Deore - VP , Data Security Council of India
Selva Kumar - Global Head-Sales, ASIP Tech
Abhijit Bhagwat - Executive Director, Renu Electronics
Chowdhary Musunuri - Sr. Director, WW FPGA, Microchip (Moderator)
Swamy Irrinki - EVP, Worldwide Sales & Marketing, MosChip
Prasad Deore - VP , Data Security Council of India
Selva Kumar - Global Head-Sales, ASIP Tech
Abhijit Bhagwat - Executive Director, Renu Electronics
Chowdhary Musunuri - Sr. Director, WW FPGA, Microchip (Moderator)
02.55 PM to 06.05 PM - Breakout sessions in Rooms .. Sabha 1, Sabha 2, Sabha 3, BRM 1, BRM 2, BRM 3, BRM 4 & BRM 5
06.05 PM to 06.30 PM - Break/Poster Session/Exhibits
6.25 PM to 6.50 PM
Banquet Speech
Dr. Amir Zjajo - Innatera
6.50 PM to 7.10 PM
Chief Guest Address
7.10 PM to 7.20 PM
Product Launch by RRP Electronics Limited
7.20 PM to 7.55 PM
Awards Ceremony
Awards Ceremony
07.55 PM to 9.25 PM
Dinner – Refuel and recharge while networking with fellow innovators.
2.55 PM to 03.15 PM
Invited talk by
Moinuddin K. Qureshi
03.15 PM to 03.35 PM
A Pipelined Probabilistic Computing Accelerator for Sparse Max-Cut with Parallel Updating p-Bits by
Kiran Magar & Utsav Banerjee
03.35 PM to 03.55 PM
An Energy Efficient Pulse Accumulator Circuit (PAC) based Multi-Bit Time Domain Compute In-Memory Architecture by
Subhradip Chakraborty & Dinesh Kushwaha
03.55 AM to 04.25 PM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
04.25 PM to 04.45 PM
Invited talk by
Nikhil Dutt
04.45 PM to 05.05 PM
An Intelligent Digital Microfluidic Biochip System with GUI and Deep Learning-Based Automation by
Sanju De, Tamal Mandal & Sudip Roy
05.05 PM to 05.25 PM
Accelerated IDP Models for Evacuation Navigation in Cyber Physical Human Environments by
Balaji Gurumurthy, Sadanand Venkataraman, Mahendravarman M, Santhi Natarajan & G Ravi Prakash Iyer
05.25 PM to 05.45 PM
QIEDP: A Quantum-Inspired Two-Bit Error Correction Protocol for Low-Power Serial Communication in IoT Systems by
Om Maheshwari & Bikram Paul
05.45 PM to 05.05 PM
A Novel VLSI Architecture and FPGA Implementation of Hardware-Efficient MFOCUSS-based Wideband Spectrum Sensor for Dynamic Spectrum Access by
Rahul Shrestha & Aayush Shrivash
2.55 PM to 03.15 PM
FPGA-based 2-phase Asynchronous Circuit Design for High Performance Computing by
Suman Kalyan Porel, Subhadeep Nag, Dr. Hemanta Kumar Mondal & Dr. Aniruddha Chandra
03.15 PM to 03.35 PM
An FPGA-Based Secure and Privacy-Aware RISC-V SoC with a CNN Accelerator for Edge AI by
Priyanshu Tyagi, Rhythm Patel, Sparsh Mittal & Rekha Singhal
03.35 PM to 03.55 PM
Design and Analysis of Fused SIM(S)D Functional Units for RISC-V P-and-B Extensions Instructions by
Nancy Gupta, DAVID SELVAKUMAR, Pranose Edavoor & GOPAL RAUT
03.55 AM to 04.25 PM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
04.25 PM to 04.45 PM
Invited talk by
Vijay Narayanan
04.45 PM to 05.05 PM
A fast-transient, low quiescent controller on a 16nm Integrated Voltage Regulator by
Anup Deka, Biswarup Rana, Shivansh Pandey & Shobhit Tyagi
05.05 PM to 05.25 PM
A Fully Integrated High-PSRR LDO with Cascaded NMOS-PMOS Buffer Architecture in 180 nm CMOS by
Anupama Kaire & Patri Sreehari Rao
05.25 PM to 05.45 PM
Thermal Runaway Analysis of Analog PIM Accelerators by
Huatao Wu & Sandip Kundu
05.45 PM to 06.05 PM
ThermLeT: Transformer-based Temperature Prediction for 2.5D Chiplet Architecture by
Varun Darshana Parekh, Anusha Devulapally, Sivani Devarapalli, Cassius Henderson, Shimeng Yu & Vijaykrishnan Narayanan
2.55 PM to 03.15 PM
MPBMC: Multi-Property Bounded Model Checking with GNN-guided Clustering by
Soumik Guha Roy, Sumana Ghosh, Ansuman Banerjee, rajkumar gajavelly & Sudhakar S
03.15 PM to 03.35 PM
A forward-backward search strategy for falsification in Spiking Neural Networks by
Sruti Goswami, Ansuman Banerjee and Swarup Kumar Mohalik
03.35 PM to 03.55 PM
A Unified BIST Framework for High-Coverage Fault Detection with Area and Power Minimization by
Athira J. Shenoy
03.55 AM to 04.25 PM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
04.25 PM to 04.45 PM
Post-Quantum HAWK Signature Acceleration with RISC-V-Based Hardware-Software Co-Design by
Rishabh Shrivastava and Utsav Banerjee
04.45 PM to 05.05 PM
Security-aware Performance-optimized Computation Offloading under Near Memory Processing by
Simran Preet Kaur, Asutosh Kumar Sarma, Satanu Maity and Manojit Ghose
05.05 PM to 05.25 PM
Machine Learning Power Side-Channel Attack on SNOW-V by
Deepak Deepak, Rahul Balout, Anupam Golder, Suparna Kundu, Angshuman Karmakar and Debayan Das
05.25 PM to 05.45 PM
RTL Information Tracker and its Applications in Quantifying the Security Impact of HLS Optimizations by
Nilotpola Sarma, Sunny Priyadarshi and Chandan Karfa
05.45 PM to 06.05 PM
Invited talk by
Debdeep Mukhopadhyay
Startup Forum - Masterclass
2.55 PM to 03.55 PM
Startup Forum - Masterclass by
Chris Rowens - VP, Cisco
03.55 AM to 04.25 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
04.25 PM to 04.45 PM
Keynote Talk by
Malini NarayanMoorthi - Country Head, Renesas India and Vice President Engineering, MID
04.45 PM to 05.05 PM
Invited talk by
Dr. Sarita Ahlawat - MD, Co-Founder, BotLab Dynamics/ Vayudh - Aviationa & Defense Manufacturing
05.05 PM to 05.35 PM
Panel Discussion : Silicon to system with AI : Women Engineering the Future.
Panel Chair - Ashlesha Karandikar, Vaishali Nair, Dr. Srobona Mitra, Prof. Maryam Baghini, Anindita Banerjee
05.35 PM to 06.05 PM
Breaking Barriers: Building Resilient Careers in Semiconductor Industry.
Panel Chair : Sana Shaikh, Monila Juneja, Madhavi Rao, Ritu Sodhi, Eleena Ong
User Design Track
AI/ Embedded Session Chair : Nanditha Rao
Logic Session Chair: Akhilesh Rathi
Analog Session Chair: Ganesh Patil
Logic Session Chair: Akhilesh Rathi
Analog Session Chair: Ganesh Patil
2.55 PM to 03.10 PM
EDGESIGHT - An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using KRIA KV260 AI-FPGA:
Senbagaseelan V, PRAVEEN R, Ragul T and Tharun Babu
3.10 PM to 03.25 PM
Efficient media processing with hybrid architecture for Edge AI applications:
Suresh Vasu, Shishira K. S. Shetty, Palanivel Guruvareddiar, Suhas Reddy and Vivek Sharma
3.25 PM to 03.40 PM
FPGA-Accelerated Adaptive Cipher Selection for Energy-Efficient Security in IoT:
Siddharth Penumatsa and Vidushi Kumar
3.40 PM to 03.55 PM
CPU Modelling Framework - Enabling Digital Twins for RISC-V Based SoC & Systems:
Umesh Sisodia and Ayush Mewati
03.55 AM to 04.25 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
4.25 PM to 04.40 PM
A Novel Approach for PCIe and AXI Domain Write Traffic Ordering - A Novel Approach:
Sathish Kumar Sivakumar, Suraj Augustine, Shibin Bose Kavara, Venkatesh Veluvolu, Atul Chauhan and Ankush Nehra
04.40 PM to 04.55 PM
Accelerating Formal Verification with RAG: Context-Aware Property Generation:
Pradip Prajapati, Anshul Jain and Zaqi Momin
04.55 PM to 05.15 PM
Security Evaluation of TI Board AES Accelerator Against Power Side-Channel Attacks:
Emlin Elsa Abraham and Anupam kumari
05.10 PM to 05.25 PM
IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems:
Neha Agrawal, Parv Malhotra, Mike Lin and Hitesh Marwah
05.25 PM to 05.40 PM
Debug at Scale: Smarter Waveform Generation for Multi-Die Datacenter Chips:
Anu Rajendran and Chris Wesneski
05.40 PM to 05.55 PM
Indias first student-built semiconductor microfabrication lab:
Anu Rajendran and Chris Wesneski
05.55 PM to 06.10 PM
A SIMO Converter for Command-Directed IoT Nodes with Fast Transient Response and Zero Cross-Regulations:
Aditi Chakraborty
06.10 PM to 06.25 PM
Adaptive Read/Write Assist augmentation for High Density SRAM ensuring reliable Ultra-Wide voltage range of operation:
Ashish Kumar and Shashank Gupta
06.25 PM to 06.40 PM
Adaptive equaliser design for efficient hardware realisation:
Sai Tejaswi P, Sanda Sai Teja Maruthi, Surya J, Shravan V, Pragati Kumari, Ansel Vivian Rego and Darshan Barma
2.45 PM to 03.45 PM
PhD Forum
1. "Advancing Spin-Orbit Torque Magnetic Tunnel Junctions for Scalable Field-Free Switching and Logic-in-Memory Architectures" by Dr. Shashidhar M
2. "Circuit Design and Architectures for Robust SRAM Compute-In-Memory" by Dr. Dinesh Kushwaha
3. "Design, Modelling and Analysis of Crossbar Array for CMOS-based Neuromorphic Integrated Circuits" by Dr. Sherin A Thomas
4. "Performance and Lifetime Enhancement of Non Volatile Memory Caches" by Dr. Sivakumar S
5. "Enhancing Security Features of Network-on-Chip Using Lightweight Cryptosystem, Trust-Aware Routing, and Anonymous Communication" by Dr. Syam Sankar
2. "Circuit Design and Architectures for Robust SRAM Compute-In-Memory" by Dr. Dinesh Kushwaha
3. "Design, Modelling and Analysis of Crossbar Array for CMOS-based Neuromorphic Integrated Circuits" by Dr. Sherin A Thomas
4. "Performance and Lifetime Enhancement of Non Volatile Memory Caches" by Dr. Sivakumar S
5. "Enhancing Security Features of Network-on-Chip Using Lightweight Cryptosystem, Trust-Aware Routing, and Anonymous Communication" by Dr. Syam Sankar
03.45 AM to 04.15 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
4.15 PM to 04.35 PM
PhD Forum
6. "Enabling In-Memory Computing With Energy Efficient Memory Architectures For AI Hardware Accelerators" by Dr. Kavitha S
7. "Design of Pipelined Architecture for Biological Sequence Alignment" by Dr. Ardhendu Sarkar
7. "Design of Pipelined Architecture for Biological Sequence Alignment" by Dr. Ardhendu Sarkar
4.35 PM to 06.25 PM
SRF Forum : 1
1. "On Cutwidth: Linear-Time Formal Verification of Circuits"A uthors: Mohamed Nadeem and Rolf Drechsler
2. "Hardware Trojans in Digital Circuits: Design, Activation, and Detection using Verilog HDL and FPGA Implementation" Authors: Riddhi Kashyap Moteria
3. "Analysis and Design of a Multi-Phase Clock Generation System for Wireline Front-End" Authors: Mayank Kumar Singh, Devarshi Mrinal Das and Mahendra Sakare
4. "The Quest for Secure Memory in the face of RowHammer" Authors: Praseetha M, Madhu Mutyam and Venkata Kalyan Tavva
5. "Application Mapping Methodologies for Optical Network-on-Chip based Manycore Processor" Authors: Sucharita Samanta and Kanchan Manna 6. "High-Throughput and Reliable Logic Computation in Partitioned-Memristive Crossbars for Processing-in-Memory Architectures" Authors: Pooja Joshi, Anindita Chakraborty and Hafizur Rahaman
7. "Formal Methods for Modeling, Verification and Interpretability of Spiking Neural Networks" Authors: Sruti Goswami, Ansuman Banerjee and Swarup Kumar Mohalik
8. "Reconfigurable High-Speed Radar Signal Processing Architecture for Integrated Sensing and Communication on System-on-Chip" Authors: Aakanksha Tewari
9. "Design and development of an efficient computation offloading strategy for NMP-enabled systems" Authors: Satanu Maity
10. "ML-Pump: A Multi-Model Bidirectional Prediction and Optimization Framework for Charge Pump Performance and Sizing" Authors: Ashutosh Singh and Anuj Grover 11. "ACCESS-AV: Adaptive Communication-Computation Codesign for Sustainable Autonomous Vehicle Localization in Smart Factories" Authors: Rajat Bhattacharjya
12. "Low Phase-Noise (-80 dBc/Hz) Adaptive FMCW Radar Transmitter with Wide Tunability at 6, 12, and 24 GHz for Drone Detection" Authors: SWETA TRIPATHI and Rakesh Kumar Palani
13. "Truly Flexible AI Processor for Analysing ECG Signals in Real-time" Authors: Vaishali Choudhary and Pydi Ganga Bahubalindruni
14. "Design of a Reconfigurable Active Inductor Based Receiver, Filter, Oscillator Architecture and Multiplier-based Sub-Terahertz Signal Generation for 5G and 6G Applications" Authors: GAURAV SRIVASTAVA and DARSHAK BHATT
15. "Next-Generation Wide-Bandgap Vertical Power Devices for High-Efficiency Renewable Integration" Authors: Rashid Jamal, Partha Sarathi Gupta and Hafizur Rahaman
16. "Deep Learning Techniques and Hardware Accelerators for Chest X-Ray Analysis in Thoracic Disorder Detection" Authors: Pawan Sharma
17. "Decentralized Framework for Teleportation in Quantum Core Interconnects" Authors: Rajeswari Suance P S, Ruchika Gupta, Maurizio Palesi and John Jose
18. "A wireless powered passive resonant-based omnidirectional sensing system for human cooperative robots (HCRs)" Authors: Vikas Kumar
19. "Hashless Eddsa via Deterministic Scalar Multiplication" Authors: Lasya Chidanand Hegde, Gautham Varma Kanumuru, Tanish Shet and Sudeendra Kumar K 20. "Post-Quantum Secure Communication Accelerator: Integrating PQC into TLS on FPGA" Authors: Chandan M, Sudeendra Kumar K, Rekha S.S, ABHAY P KALGHATKAR, Amodini K and BHUVAN S
21. "Custom Crypto Co-Processor IP for RISC -V Processor" Authors: Ishan Nilesh Upadhye
22. "DESIGN AND ANALYSIS OF HYBRID CMOS/MTJ CIRCUITS WITH APPLICATIONS" Authors: SAHAANA KANAGESAN and KAMALA J
23. "A Smart Earring Platform for Continuous Multi-Parameter Physiological Monitoring: Design, Validation, and Clinical Applications" Authors: Avinash Ankush Kshirsagar and Shailesh Shamrao Parab
24. "Strain and Doping-Engineered WS2 for High-Performance Thermoelectric Applications: A DFT and Machine Learning Approach" Authors: AJOY KUMAR SAHA
2. "Hardware Trojans in Digital Circuits: Design, Activation, and Detection using Verilog HDL and FPGA Implementation" Authors: Riddhi Kashyap Moteria
3. "Analysis and Design of a Multi-Phase Clock Generation System for Wireline Front-End" Authors: Mayank Kumar Singh, Devarshi Mrinal Das and Mahendra Sakare
4. "The Quest for Secure Memory in the face of RowHammer" Authors: Praseetha M, Madhu Mutyam and Venkata Kalyan Tavva
5. "Application Mapping Methodologies for Optical Network-on-Chip based Manycore Processor" Authors: Sucharita Samanta and Kanchan Manna 6. "High-Throughput and Reliable Logic Computation in Partitioned-Memristive Crossbars for Processing-in-Memory Architectures" Authors: Pooja Joshi, Anindita Chakraborty and Hafizur Rahaman
7. "Formal Methods for Modeling, Verification and Interpretability of Spiking Neural Networks" Authors: Sruti Goswami, Ansuman Banerjee and Swarup Kumar Mohalik
8. "Reconfigurable High-Speed Radar Signal Processing Architecture for Integrated Sensing and Communication on System-on-Chip" Authors: Aakanksha Tewari
9. "Design and development of an efficient computation offloading strategy for NMP-enabled systems" Authors: Satanu Maity
10. "ML-Pump: A Multi-Model Bidirectional Prediction and Optimization Framework for Charge Pump Performance and Sizing" Authors: Ashutosh Singh and Anuj Grover 11. "ACCESS-AV: Adaptive Communication-Computation Codesign for Sustainable Autonomous Vehicle Localization in Smart Factories" Authors: Rajat Bhattacharjya
12. "Low Phase-Noise (-80 dBc/Hz) Adaptive FMCW Radar Transmitter with Wide Tunability at 6, 12, and 24 GHz for Drone Detection" Authors: SWETA TRIPATHI and Rakesh Kumar Palani
13. "Truly Flexible AI Processor for Analysing ECG Signals in Real-time" Authors: Vaishali Choudhary and Pydi Ganga Bahubalindruni
14. "Design of a Reconfigurable Active Inductor Based Receiver, Filter, Oscillator Architecture and Multiplier-based Sub-Terahertz Signal Generation for 5G and 6G Applications" Authors: GAURAV SRIVASTAVA and DARSHAK BHATT
15. "Next-Generation Wide-Bandgap Vertical Power Devices for High-Efficiency Renewable Integration" Authors: Rashid Jamal, Partha Sarathi Gupta and Hafizur Rahaman
16. "Deep Learning Techniques and Hardware Accelerators for Chest X-Ray Analysis in Thoracic Disorder Detection" Authors: Pawan Sharma
17. "Decentralized Framework for Teleportation in Quantum Core Interconnects" Authors: Rajeswari Suance P S, Ruchika Gupta, Maurizio Palesi and John Jose
18. "A wireless powered passive resonant-based omnidirectional sensing system for human cooperative robots (HCRs)" Authors: Vikas Kumar
19. "Hashless Eddsa via Deterministic Scalar Multiplication" Authors: Lasya Chidanand Hegde, Gautham Varma Kanumuru, Tanish Shet and Sudeendra Kumar K 20. "Post-Quantum Secure Communication Accelerator: Integrating PQC into TLS on FPGA" Authors: Chandan M, Sudeendra Kumar K, Rekha S.S, ABHAY P KALGHATKAR, Amodini K and BHUVAN S
21. "Custom Crypto Co-Processor IP for RISC -V Processor" Authors: Ishan Nilesh Upadhye
22. "DESIGN AND ANALYSIS OF HYBRID CMOS/MTJ CIRCUITS WITH APPLICATIONS" Authors: SAHAANA KANAGESAN and KAMALA J
23. "A Smart Earring Platform for Continuous Multi-Parameter Physiological Monitoring: Design, Validation, and Clinical Applications" Authors: Avinash Ankush Kshirsagar and Shailesh Shamrao Parab
24. "Strain and Doping-Engineered WS2 for High-Performance Thermoelectric Applications: A DFT and Machine Learning Approach" Authors: AJOY KUMAR SAHA
Tape-out Contest
2.55 PM to 03.15 PM
A 39 GHz Transmit–Receive Front-End Module for 5G Application.
Dr Nagarjuna Nallam, Dr Mahima Arrawatia and Uday Maurya, IIT Guwahati
03.15 PM to 03.35 PM
Integrated Circuit Wideband RF Delay-line in 65nm CMOS
Mohmad Aasif Bhat, IIT Kanpur
03.35 PM to 03.55 PM
A 2.7-15.5 GHz Programmable Bandwidth Continuous-Time Active Filter in 65
Mayank Anupam, IIT Kanpur
3.55 PM to 4.25 PM
BREAK
04.25 PM to 04.45 PM
Ultra Low Reference Spur Sub-Sampling Phase-Locked Loop
Anshul Verma, IIT Roorkee
04.45 PM to 05.05 PM
A 189.1 dBc/Hz FoM Ku-Band Triple-Coil Transformer VCO with Harmonic-Rich Shaping, Gm-Boosting, and Noise Circulation in 65 nm CMOS
Narahari N. Moudhgalya, IIIT Hyderabad
Registration - 8:00 AM to 9:30 A.M.
09.30 AM to 09.50 AM
Keynote Address (KD3-1)
Prof. Debdeep Mukhopadhyay - IIT Kharagpur
09.50 AM to 10.10 AM
Keynote Address (KD3-2)
Biswadeep Chatterjee - Associate VP, Semiconductor Business, HCLTech
10.10 AM to 10.30 AM
Keynote Address (KD3-3)
Lenin Patra - SVP Platform and Switch Architecture, Marvell
10.30 AM to 11.20 AM
Panel Discussion - AI Powered EDA - Revolutionizing Chip Design for Tomorrow
Amit Khanuja - VP, R&D Engineering, IP Group, Synopsys
Dr. Preetham Lakshmikanthan - VP Technology and Growth , Proxelera
Vikram Somaiya - Senior Director ASIC Development Engineering , Sandisk
Dieter Therssen - CEO, Sigas
Dr. Ashish Darbari - Founder and CEO, Axiomise (Moderator)
Dr. Preetham Lakshmikanthan - VP Technology and Growth , Proxelera
Vikram Somaiya - Senior Director ASIC Development Engineering , Sandisk
Dieter Therssen - CEO, Sigas
Dr. Ashish Darbari - Founder and CEO, Axiomise (Moderator)
11.20 AM to 11.40 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.40 AM to 12.30 AM
Panel Discussion - Future-Ready Semiconductor Talent for the world
Pradeep Vajram - Founder & CEO 7-Rays (Moderator)
Bhimender Saini - AVP Quest Global
Anand Muthaiah - SVP, Test Engineering and Head of COE, Tessolve
Prof.Pawan Sharma - BITS Pilani
Sanjay Wandekar - Center Head, CDAC Pune
Murty Dasaka - VP, TEPL
Bhimender Saini - AVP Quest Global
Anand Muthaiah - SVP, Test Engineering and Head of COE, Tessolve
Prof.Pawan Sharma - BITS Pilani
Sanjay Wandekar - Center Head, CDAC Pune
Murty Dasaka - VP, TEPL
12.30 PM to 1.30 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
01.40 PM to 02.00 PM
Fireside Chat - Bridging the gap between Academia and Industry
Dr.Shivanand Koteshwar - India MD, Astera Labs
Dr. S D Sudarsan - Executive Director CDAC
Dr. S D Sudarsan - Executive Director CDAC
02.00 PM to 06.10 PM - Breakout sessions in Rooms .. Sabha 1, Sabha 2, Sabha 3, BRM 1, BRM 2, BRM 3, BRM 4 & BRM 5
2.00 PM to 02.20 PM
MIRAGE: Micro-Ring-Accelerated General Engine with Phase-Error Compensation for Scalable Full-Range Matrix-Vector Multiplication by
PRIYABRATA DASH and Dharanidhar Dang
02.20 PM to 02.40 PM
Self-Heating Aware Performance Investigation of Vertically and Sideway Stacked GAA Nanowire FETs at Sub-5nm Technology Node by
Guruprasad Reddy, Jagan V, Shashidhara M, Shobhit Srivastava and Abhishek Acharya
02.40 PM to 03.00 PM
Adaptive t-Design Dummy-Gate Obfuscation for Cryogenic-Scale Enforcement by
Samuel Thomas Punch and Krishnendu Guha
03.00 PM to 03.20 PM
Balanced Cascade: Free-Flowing Microfluidic Lab-on-Chip for Generating Serial Dilutions by
Tapalina Banerjee, Sudip Poddar and Bhargab B. Bhattacharya
3.20 PM to 3.50 PM
BREAK
03.50 PM to 04.10 PM
Low-Power Tunable Band-Pass Filter Using Unipolar Oxide TFT Technology for Wearable Applications. by
Vaishali Choudhary, Suyash Shrivastava and Pydi Ganga Bahubalindruni
04.10 PM to 04.30 PM
A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation based Equalization and Analog Echo Canceller by
Saurabh Saxena, Vinod Ganesan and Shubham Choudhary
04.30 PM to 04.50 PM
Scaling Limits and Reliability Challenges of Nanoscale GaN HEMTs: A Path Toward Advanced Node Benchmarking for DC and RF applications by
Shivansh Awasthi, Vikas Kumar and Ankur Gupta
04.50 PM to 05.10 PM
CAD-Enabled pH Control Optimization for Digital Microfluidic Lab-on-Chips by
Sumanta Pyne and Bhargab Bhattacharya
05.10 PM to 05.30 PM
LeakAnalyser: Uncertainty-Aware Analysis of Leakage Power in Digital Circuits under PVT Variations by
Sarang Kudtarkar and Zia Abbas
05.30 PM to 05.50 PM
Exploring the Resilience Nature of AlN Cap Layer in AlGaN/GaN HEMT under Thermal Conditions by
Mr. Ellapu Bhanu Prakash, Dr. Ashok Ray and Dr. Sushanta Bordoloi
05.50 PM to 06.10 PM
DP-VSA: DSP Packing-based Vector Systolic Accelerator With Dual Precision Support on FPGAs by
Aashish Kumar Tiwary, Yathin Kumar Attuluri and Nanditha Rao
02.00 PM to 02.20 PM
A 146 GOPS and 7.2 TOPS/W 6T SRAM-Based Analog CIM Macro using Bit-splitting for 8-Bit MAC Operations by
CHEENA SINGHAL, Abhishek Goel, Sparsh Mittal and Sudeb Dasgupta
02.20 PM to 02.40 PM
Flash-based Dynamic Dot Product Acceleration by
Kyler R. Scott and Sunil P. Khatri
02.40 PM to 03.00 PM
RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN by
Mohd Faisal Khan, Mukul Lokhande and Santosh Vishvakarma
03.00 PM to 03.20 PM
Design and FPGA Implementation of Power and Area Efficient Multi-Stage Accelerator for Depthwise Separable Convolutions by
Rahul Shrestha and Srishti Misra
3.20 PM to 3.50 PM
BREAK
03.50 PM to 04.10 PM
Partial Product Grouping-Based Approximate Multipliers for Deep Learning Inference by
Samarpana Boggu Priestly, Siddharth R. K., Geeta Shet, Vasantha M.H. and Nithin Kumar Y.B.
04.10 PM to 04.30 PM
IncepLite: An FPGA Based Inceptionet Accelerator for ECG Classification at Edge Devices by
Anju Yajjala, Muralidhar Pullakandam and Gopala Krishna Thota
4.30 PM to 04.50 PM
ASIC Design for a Hybrid Approximate Floating-Point Adder with Enhanced Carry Prediction Logic by
Sridhar C and Aniruddha Kanhe
04.50 PM to 05.10 PM
Temporal Data Encoding and On-Chip Training of an SNN for ECG Classification by
Saras Mani Mishra, Hanumant Singh Shekhawat and Gaurav Trivedi
05.10 PM to 05.30 PM
UniGD: A Unified Pipelined FPGA Accelerator for Analytical and Numerical Gradient Descent in Edge AI by
Prachi A. Mukherji, Seema H. Rajput and Nandini R. Kendre
05.30 PM to 05.50 PM
Modeling Supercapacitors for Longer Battery Life of Cardiac Pacemakers by
Sumanta Pyne
05.50 PM to 06.10 PM
A Capacitorless On-Chip LDO for Jitter Reduction in 7.2Gbps HBM3E PHY Clock Network with Aging and Power Delivery Analysis by
Javed S. Gaggatur
2.00 PM to 02.20 PM
Cost and Communication-aware Fast Placement of Processing Elements in Chiplets for 2.5D Systems by
Ayman Un Nisa, Ashok Jagannathan and Sumit K. Mandal
02.20 PM to 02.40 PM
Universal Formal Verification Approach for Modular Reduction Circuits by
Jiteshri Dasari and Maciej Ciesielski
02.40 PM to 03.00 PM
A Transistor-level Implementation of Radix-2 and Radix-4 FFT Using Logical Effort by
Harsh Raj Thakur and Sparsh Mittal
03.00 PM to 03.20 PM
Spike-Based Time-Domain ECG Wave Delineation for Low-Power VLSI Implementation by
Priya K and Binsu Kailath
3.20 PM to 3.50 PM
BREAK
03.50 PM to 04.10 PM
Cadence Design Systems - Redefining SoC Design: The Shift to Chiplet-Based Architecture by
Moshiko Emmer - Distinguished Engineer, Silicon Solution Group
04.10 PM to 04.30 PM
LeadSoC - Anyone Can Design VLSI IP Now, Responsible AI Methodologies Empowering the Next-Gen Designer by
Veena S Chakravarthi - Director, LeadSOC Technologies India, Senior IEEE Member
04.30 PM to 04.50 PM
Ramtera - "LVR: Scalable Distributed DRC for 1-Trillion-Polygon Designs” by
Mr. Sameer Pawanekar - Founder and CEO
04.50 PM to 05.10 PM
Meta - Achieving Best PPA for Next Gen METAs Inference Accelerator by
Dheepak Jayaraman, Harish Aepala - ASIC Engineering Manager
05.10 PM to 05.30 PM
Texas Instruments - Intelligent Radar-based Low Power Presence Sensing Solution for Broad Market Applications by
Praveen Natarajan - Radar & Perception SW Lead (R&D)
05.30 PM to 05.50 PM
Qualcomm L2Pro (Learn to Protect IPR) and AI Upskilling by
Souvik Basu
TAPE OUT Contest.
2.00 PM to 02.20 PM
TAPE OUT Contest
02.20 PM to 02.40 PM
TAPE OUT Contest
02.40 PM to 03.00 PM
TAPE OUT Contest
03.00 PM to 03.20 PM
TAPE OUT Contest
3.20 PM to 3.50 PM
BREAK
03.50 PM to 04.10 PM
TAPE OUT Contest
04.10 PM to 04.30 PM
TAPE OUT Contest
04.30 PM to 04.50 PM
TAPE OUT Contest
04.50 PM to 05.10 PM
TAPE OUT Contest
05.10 PM to 05.30 PM
TAPE OUT Contest
05.30 PM to 05.50 PM
TAPE OUT Contest
05.50 PM to 06.10 PM
Design Contest
2.00 PM to 03.20 PM
Platform 1: Lattice Semiconductors CPNX VVML FPGA:
1. FPGA-Based CNN Accelerator Integrated with RISC-V SoC for Silicon Wafer Defect Classification
by Priyanshu Tyagi & Sparsh Mittal (IIT Roorkee), Rhythm Patel (SVNIT Surat)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
Platform 2: Microchip Technologys PolarFire SoC Icicle Kit:
1. TRINETRA: Seeing Beyond Vision
by Akshat Sharma, Tanvi R, Dr. Chethana G (RV College of Engineering)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
Platform 3: Qubit Designing using Qiskit Metal:
1. Readout-Optimized Transmon Qubit as a Quantum Front-End for VLSI Decoding Accelerators.
by Aman Raj Saurav, Priyam Mishra, Tushar Garg, Satyam Chauhan, Prof Jawar Singh (Indian Institute of Technology Patna)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
3.20 PM to 3.50 PM
BREAK
2.00 PM to 03.20 PM
Platform 1: Lattice Semiconductors CPNX VVML FPGA:
1. FPGA-Based CNN Accelerator Integrated with RISC-V SoC for Silicon Wafer Defect Classification
by Priyanshu Tyagi & Sparsh Mittal (IIT Roorkee), Rhythm Patel (SVNIT Surat)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
2. LifeFinder:FPGA-Powered Drone for Disaster Rescue by D. Srikarani, Akshaya Pawar, Dr. Mudasar Basha (B V Raju Institute of Technology)
3. FPGA-Based Real-Time Sensor Fusion System for Autonomous Vehicles (Camera + Ultrasonic) by CHAITRIKA KONDA, ALEKHYA KORIVI, KRUPALAXMI KONDA, VINAY REDDY KONGARI, PAVANKUMAR BIKKI (BVRIT-Narsapur)
4. GLOBAL MULTI-PURPOSE INTRUDER & WILDLIFE MONITORING SYSTEM USING LATTICE FPGA + AI/ML + MULTI-SENSOR FUSION by Senthil Kumar Mahalingam, JHOTHEESHWAR S S, Ramaprakash B, PRIYADHARSAN D, Malini P (Chennai Institute of Technology)
5. Pedestrian Detection and alert system using FPGA by Aditya Jahagirdar, Prathamesh Modod, yash.kaleparshuram Deshpande, Siddhesh Kulkarni (VIT Pune)
6. FPGA-Based Multimodal Industrial Defect Detection System by Hrishikesh Jagdale, Anagh Mishra, Samiksha khot, Iosham Sharma, Dr. Anuja Askhedkar (MIT Pune)
7. FPGA Based Hardware Realization of 24-Bit ADC Interface Using SPI Protocol by Shraddha Magar, Tejal Chaudhari, Shruti Pawashe, Abhijit Jamdade, Umashankar More (Dnyanashree Institute of Engineering and Technology)
Platform 2: Microchip Technologys PolarFire SoC Icicle Kit:
1. TRINETRA: Seeing Beyond Vision
by Akshat Sharma, Tanvi R, Dr. Chethana G (RV College of Engineering)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
2.EdgeSight: An FPGA-Accelerated AI Assistive Device for the Visually Impaired Using PolarFire® SoC FPGA by Senbagaseelan V, Ragul T, Praveen R, Tharun Babu, Dr.Bommi R.M. (Chennai Institute of Technology)
3. AI-Based Defect Detection and Smart Rejection for Industrial Automation by Joel Philip, Shravan Sunil, Amruth Gulawani, Amritha Anujan, Kala S (Indian Institute of Information Technology Kottayam)
4. An FPGA-Accelerated AI-Assisted Precision Remote-Controlled Perimeter Security System (PRC-PSS) for Enhanced Border Security by Adhish JS, Nallamothu Balakrishna, Vijaya Kumar K, Suresh Balanethiram (National Institute of Technology Puducherry)
5. Real-Time Breath Rate Monitoring for Healthcare Using Microchip PolarFire® SoC Icicle Kit by Ethesham Ahmed, Aiman Malik, Dr. Mohd Wajid (Aligarh Muslim university)(VIT Pune)
Platform 3: Qubit Designing using Qiskit Metal:
1. Readout-Optimized Transmon Qubit as a Quantum Front-End for VLSI Decoding Accelerators.
by Aman Raj Saurav, Priyam Mishra, Tushar Garg, Satyam Chauhan, Prof Jawar Singh (Indian Institute of Technology Patna)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
2. Optimisation and Crosstalk Analysis of a Two-Qubit System with a Tunable Coupler by Akash B, Leninsingaram G, Potri Selvan K, Pravinraj T (PSG Institute of Technology and Applied Research)
3. 4-Qubit Flip-Chip Transmon for Behavioral Fraud Detection by SANJAY S, MANEES KUMAR T, MANOJ KUMAR T, JAYAPRAKASH A, Md Manirul Ali (Chennai institute of Technology)
4. Physical Implementation of a Quantum Repetition Code using Qiskit Metal by Niranjan Nagumalli, Ravi Theja Kolluru, Mayank Goel, Dheeraj Gandepalli, Lalitha Vadlamani (IIIT Hyderabad)
5. SQUID-based Xmon Qubit for Enhanced QND Single-Photon Detection in the QUB-IT Experiment by Uday Mathur, Fizaan Khaan, Rajeev Singh (Indian Institute of Technology (BHU), Varanasi)
Startup Forum
2.00 PM to 02.40 PM
Startup Masterclass: Support Infrastructure for Semiconductor Startups in India
Ajay Prasad Shrivastava - Director, STPI, Pune
02.50 PM to 03.30 PM
Startup Forum: Pitch Competition
3.30 PM to 4.00 PM
BREAK
04.00 PM to 05.00 PM
Startup Forum: Pitch Competition
05.00 PM to 05.40 PM
Startup Forum: Pitch Competition