Skip to content

Agenda

Day 1 Sat, Jan 2 · Tutorials
09:00–10:30

Welcome & Registration Reg

10:30–12:30

Tutorial A: Advanced Verification with UVM Tutorial

Hands-on session covering coverage-driven verification and constrained random testing.

12:30–13:30

Lunch

13:30–15:30

Tutorial B: RISC-V Processor Design from RTL to Silicon Tutorial

End-to-end flow: HDL, synthesis, place-and-route, sign-off, and tape-out checklist.

15:30–16:00

Coffee Break

16:00–18:00

Tutorial C: ML Accelerator Architecture Tutorial

Dataflow design, sparsity, low-precision arithmetic, and benchmark comparisons.

Day 2 Sun, Jan 3 · Workshops
09:00–10:30

Workshop W1: Open-Source Silicon & Chiplets Workshop

Industry-academia panel on open standards, OpenROAD, and chiplet interconnect.

10:30–11:00

Coffee Break

11:00–12:30

Workshop W2: Hardware Security in Modern SoCs Workshop

Side-channel attacks, secure boot, root-of-trust, post-quantum considerations.

12:30–13:30

Lunch

13:30–15:30

Workshop W3: AI-Driven EDA Flows Workshop

How LLMs and reinforcement learning are reshaping floor-planning and verification.

15:30–18:00

Industry Booth Walkthrough

Visit sponsor booths; meet recruiters from leading semiconductor firms.

Day 3 Mon, Jan 4 · Main Conference
09:00–09:30

Inauguration & Welcome Address

09:30–10:30

Keynote 1: The Next Decade of Semiconductor Design Keynote

Visionary talk from a leading industry executive.

10:30–11:00

Coffee Break

11:00–12:30

Session 1A: Analog & Mixed-Signal Circuits Papers

Four peer-reviewed paper presentations.

11:00–12:30

Session 1B: Embedded ML & Edge AI Papers

Parallel track. Four peer-reviewed paper presentations.

12:30–13:30

Lunch & Poster Session

13:30–15:00

Industry Panel: From Lab to Fab Panel

Cross-industry discussion on commercializing research silicon.

15:00–16:30

Session 2: Hardware Security & Reliability Papers

18:30–21:00

Welcome Reception

Day 4 Tue, Jan 5 · Main Conference
09:00–10:00

Keynote 2: Beyond Moore — Architecting the Post-CMOS Era Keynote

10:00–10:30

Coffee Break

10:30–12:30

Session 3: Processor Architectures Papers

12:30–13:30

Lunch

13:30–15:00

Design Contest Finals Contest

Top student teams present their silicon designs.

15:30–17:00

Session 4: EDA & CAD Innovation Papers

19:00–22:00

Conference Banquet & Awards

Day 5 Wed, Jan 6 · Main Conference
09:00–10:00

Keynote 3: The Future of Embedded Intelligence Keynote

10:00–10:30

Coffee Break

10:30–12:00

Session 5: Emerging Technologies Papers

12:00–13:00

Lunch

13:00–14:30

Session 6: AI/ML Hardware Papers

14:30–15:30

Best Paper Awards & Closing Ceremony

15:30–16:30

Farewell Networking

Schedule subject to change. Final program will be published 2 weeks before the conference.

Lock in Your Seat

Register Before Early Bird Closes

All registered delegates receive access to every session, lunches, the welcome reception, and the conference banquet.

Have Questions?

Connect with the VLSID 2027 Team

For specific queries on tracks, papers, or sponsorships, reach out to the organizing team directly at info@vlsid.org.