{"id":1561,"date":"2023-09-04T15:03:20","date_gmt":"2023-09-04T15:03:20","guid":{"rendered":"https:\/\/vlsid.org\/?page_id=1561"},"modified":"2023-12-16T21:37:21","modified_gmt":"2023-12-16T21:37:21","slug":"user-design-track","status":"publish","type":"page","link":"https:\/\/vlsid.org\/user-design-track\/","title":{"rendered":"User Design Track"},"content":{"rendered":"\n<h3 class=\"wp-block-heading has-text-align-center\">Important Dates<\/h3>\n\n\n\n<div class=\"wp-block-getwid-section alignfull getwid-margin-top-none getwid-margin-bottom-none getwid-section-content-full-width\"><div class=\"wp-block-getwid-section__wrapper getwid-padding-top-none getwid-padding-bottom-none getwid-padding-left-none getwid-padding-right-none getwid-margin-left-none getwid-margin-right-none getwid-reset-min-height-tablet getwid-reset-min-height-mobile\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<h6 class=\"wp-block-heading has-text-align-center has-palette-color-4-color has-text-color\">Final date of submission : Is Now Closed <br>Notification for Acceptance: 15th December, 2023<br>Final PPT Submission: 22nd December, 2023 <br>Final Presentation : The date will be announced soon <\/h6>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<br><br><style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-color:#93a1a1;border-spacing:0;margin:0px auto;}\n.tg td{background-color:#fdf6e3;border-color:#93a1a1;border-style:solid;border-width:1px;color:#002b36;\n  font-family:Arial, sans-serif;font-size:14px;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{background-color:#657b83;border-color:#93a1a1;border-style:solid;border-width:1px;color:#fdf6e3;\n  font-family:Arial, sans-serif;font-size:14px;font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-zriu{background-color:#003532;border-color:inherit;color:#ffffff;font-weight:bold;position:-webkit-sticky;position:sticky;\n  text-align:center;top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-eb5z{background-color:#036400;border-color:inherit;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-0pky{border-color:inherit;text-align:left;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-zriu\" colspan=\"3\">User   Design Track<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-eb5z\" width=\"10%\">No.<\/td>\n    <td class=\"tg-eb5z\" width=\"45%\">Title   of the Submission<\/td>\n    <td class=\"tg-eb5z\" width=\"45%\">Name<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">1<\/td>\n    <td class=\"tg-0pky\">A&nbsp;&nbsp;&nbsp;4Ghz SRAM in 3nm with novel DFT scheme to improve at speed fault coverage<\/td>\n    <td class=\"tg-0pky\">Sriharsha   Enjapuri, Manish Trivedi, Deepesh Gujjar, Jaswinder Singh, Sandipan Sinha and   Ramesh Halli<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">2<\/td>\n    <td class=\"tg-0pky\">ATE&nbsp;&nbsp;&nbsp;Testing for Complex Memory at 7nm &#8211; DFT insights covering Peak-Power, Testing&nbsp;&nbsp;&nbsp;&amp; Issues<\/td>\n    <td class=\"tg-0pky\">Jaykumar&nbsp;&nbsp;&nbsp;Goraseeya and Raj Gandhi<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">3<\/td>\n    <td class=\"tg-0pky\">TinyML&nbsp;&nbsp;&nbsp;System for Detecting Life-Threatening Ventricular Arrhythmias<\/td>\n    <td class=\"tg-0pky\">Vipin&nbsp;&nbsp;&nbsp;Gautam, Sharad Sinha and Shitala Prasad<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">4<\/td>\n    <td class=\"tg-0pky\">Modulating&nbsp;&nbsp;&nbsp;Free Layer of Magnetic Tunnel Junction : A Novel Approach for&nbsp;&nbsp;&nbsp;Energy-Efficient Computing in Memory<\/td>\n    <td class=\"tg-0pky\">Alisha B ,  Dr. Tripti S. Warrier<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">5<\/td>\n    <td class=\"tg-0pky\">Robust&nbsp;&nbsp;&nbsp;Noise Immune Inverting Schmitt Trigger for Radiation Exposed Environment<\/td>\n    <td class=\"tg-0pky\">Aryan Kannaujiya, Ambika Prasad Shah<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">6<\/td>\n    <td class=\"tg-0pky\">CRVPGen&nbsp;&nbsp;&nbsp;: C-Random verification programs for Processor design validation<\/td>\n    <td class=\"tg-0pky\">Srinivasa Tipparaju, Rishna Patteri, Bijay Sharma and Karun Talari<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">7<\/td>\n    <td class=\"tg-0pky\">Efficient&nbsp;&nbsp;&nbsp;Workload Optimization for CPU-GPU Co-Design in Intelligent Cyber-Physical&nbsp;&nbsp;&nbsp;Systems<\/td>\n    <td class=\"tg-0pky\">Ashiqur &nbsp;&nbsp;&nbsp;Molla, Suraj Singh, Srijeeta Maity and Soumyajit Dey<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">8<\/td>\n    <td class=\"tg-0pky\">Process&nbsp;&nbsp;&nbsp;Mismatch Tolerant Adaptive Read Assist for SRAM using Replica Bias Control<\/td>\n    <td class=\"tg-0pky\"> Ashish Kumar<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">9<\/td>\n    <td class=\"tg-0pky\">Advance&nbsp;&nbsp;&nbsp;and Comprehensive Debug (Ad-Code)<\/td>\n    <td class=\"tg-0pky\">Anmol&nbsp;&nbsp;&nbsp;Khatri, Soumik Mukherjee, Praveen Chinta and Lalit Arora<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">10<\/td>\n    <td class=\"tg-0pky\">SPARC&nbsp;&nbsp;&nbsp;&#8211; An intelligent autonomous flow for power switch Selection, Placement, Auto&nbsp;&nbsp;&nbsp;Routing and Connectivity optimization<\/td>\n    <td class=\"tg-0pky\">Subbash&nbsp;&nbsp;&nbsp;K P, Pardhu Pavan S and Vikash K T<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">11<\/td>\n    <td class=\"tg-0pky\">Low-cost,&nbsp;&nbsp;&nbsp;Power IR drop consideration methodology for high contact resistance in&nbsp;&nbsp;&nbsp;advanced technologies nodes for robust memory design and accurate&nbsp;&nbsp;&nbsp;characterization.<\/td>\n    <td class=\"tg-0pky\">Praveen&nbsp;&nbsp;&nbsp;Kumar Verma, Anuj Dhillon, Harshit Sharma and Vartul Sharma<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">12<\/td>\n    <td class=\"tg-0pky\">Approximate&nbsp;&nbsp;&nbsp;CNN for Edge Computing<\/td>\n    <td class=\"tg-0pky\">Abhinav&nbsp;&nbsp;&nbsp;K, Nalesh S and Kala S<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">13<\/td>\n    <td class=\"tg-0pky\">FastMiner-Design&nbsp;&nbsp;&nbsp;and Implementation of FPGA accelerated Bitcoin Miner<\/td>\n    <td class=\"tg-0pky\">Mayank&nbsp;&nbsp;&nbsp;Kabra, Harshita Gupta, Asmita Zjigyasu and Madhav Rao<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0pky\" style=\"text-align:center\">14<\/td>\n    <td class=\"tg-0pky\">System-Level&nbsp;&nbsp;&nbsp;Modeling for Real-Time DNN Inference on Edge Devices<\/td>\n    <td class=\"tg-0pky\">Tom&nbsp;&nbsp;&nbsp;Jose and Deepak Shankar<\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n\n\n\n<h3 class=\"wp-block-heading has-text-align-center\">Important Link<\/h3>\n\n\n\n<div class=\"wp-block-buttons is-content-justification-center is-layout-flex wp-container-1\">\n<div class=\"wp-block-button has-custom-font-size is-style-fill has-small-font-size\"><a class=\"wp-block-button__link has-ethernal-constance-gradient-background has-background has-text-align-center wp-element-button\" href=\"https:\/\/softconf.com\/n\/vlsid2024_user\" style=\"border-radius:5px\" target=\"_blank\" rel=\"noreferrer noopener\">Submit UDT PPT<\/a><\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading has-text-align-center\"> Topics<\/h3>\n\n\n\n<div class=\"wp-block-getwid-section alignfull alignfull getwid-section-content-custom-width\"><div class=\"wp-block-getwid-section__wrapper\" style=\"padding-top:1px;padding-bottom:6px;padding-left:1px;padding-right:2px\"><div class=\"wp-block-getwid-section__inner-wrapper\" style=\"max-width:936px\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-getwid-section getwid-section-content-full-width\"><div class=\"wp-block-getwid-section__wrapper\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\" style=\"opacity:0.44\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-columns is-layout-flex wp-container-5\">\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Artificial Intelligence, Machine Learning and their Applications<\/h6>\n\n\n\n<p style=\"text-align: justify;\">AI Accelerators, Edge Computing, Approximate Computing, Autonomous Intelligence (ADAS), AI ethics.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Security and Safety<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Functional Safety, Privacy, Cryptography, PUFs, TRNGs, Hardware Trojans, Trusted Computing, Network Security, Side-Channel and Fault Analysis and Countermeasures.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Analog and Mixed Signal Design<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Analog Circuits for Various Applications, Data Converters, High Speed Interfaces, Power Management Circuits, Energy Harvesting Circuits &amp; Systems, Circuits &amp; Systems for AI-oriented Applications.<\/p>\n<\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-section\"><div class=\"wp-block-getwid-section__wrapper\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-columns is-layout-flex wp-container-9\">\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Sensors Circuits and Systems<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Autocalibration Techniques, Wearable Electronics, Autonomous Sensors Systems.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Digital Integrated Circuits and Systems<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Digital Circuits for Communication, Arithmetic Circuits, System-on-Chip Design, Network-on-Chip Design, Low-power Logic Design.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Power Electronics<\/h6>\n\n\n\n<p style=\"text-align: justify;\">High Power Circuits, Power Convertors, Power Optimization Techniques, Power Delivery Networks, Power Switches, High Voltage Circuits and Systems, Power Management for High Voltage Applications, Power Amplifiers.<\/p>\n<\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-section\"><div class=\"wp-block-getwid-section__wrapper\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-columns is-layout-flex wp-container-13\">\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Low power Digital Architectures<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">RF Circuits and Systems<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Transceiver Architectures, Short-Range Communication, IoT\/IoE, WPAN, Ultra-Low Power Wireless Designs, Effective Spectrum Utilization, RF Power Amplifiers, RF Energy Harvesting.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Emerging Technologies and Devices<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Quantum Computing, Neuromorphic Computing, Synaptic Devices, CMOS Technology and Devices, New Age Nano-Electronics, MEMS Devices, GaN and SiC Devices.<\/p>\n<\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-section\"><div class=\"wp-block-getwid-section__wrapper\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-columns is-layout-flex wp-container-17\">\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Test and Reliability<\/h6>\n\n\n\n<p style=\"text-align: justify;\">EMIR, Interconnect, Power Integrity-Signal Integrity (PISI), EMI\/EMC Compatibility, Built-in Self-Test, Design for Test, Self-X (Awareness, Repair, Test), On-line Test, Fault Tolerance.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Embedded System Design<\/h6>\n\n\n\n<p style=\"text-align: justify;\">IoT Systems, Cyber-Physical Systems, Hardware\/Software Co-design, Embe-&nbsp; dded Software, Embedded Operating Systems .<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Architectures<\/h6>\n\n\n\n<p style=\"text-align: justify;\">Chip Architecture, Computer Architecture, High Performance Computing, Configurable Computing, (Embedded) FPGA, Memory Subsystems, In Memory Computing Systems.<\/p>\n<\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-section\"><div class=\"wp-block-getwid-section__wrapper\" style=\"padding-bottom:0px\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-columns is-layout-flex wp-container-21\">\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\"><strong>Electronic Design Automation<\/strong><\/h6>\n\n\n\n<p style=\"text-align: justify;\">Verification, Synthesis, Physical Design, Silicon Engineering, Just-in-time Synthesis, AI enabled algorithms, Formal Verification, Optimization.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\">\n<h6 class=\"wp-block-heading\">Packaging and Interconnects<\/h6>\n\n\n\n<p style=\"text-align: justify;\">On-chip interconnects, 3D packaging, Wafer-level packaging, Interconnect Technologies.<\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow\"><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-section alignfull justifyText alignfull getwid-section-content-custom-width\"><div class=\"wp-block-getwid-section__wrapper getwid-padding-left-medium getwid-padding-right-medium\"><div class=\"wp-block-getwid-section__inner-wrapper\" style=\"max-width:740px\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-getwid-advanced-heading has-custom-font-size\" style=\"font-size:21px;margin-bottom:15px;margin-top:6px\"><h2 class=\"wp-block-getwid-advanced-heading__content\" style=\"text-align:center\">Please Note<\/h2><\/div>\n\n\n\n<ul class=\"justifyText\">\n<li>All presentation submissions to User Design Track should be made electronically via the below submit button before the due date.<\/li>\n\n\n\n<li>Use provided presentation template only. You can download presentation template below.<\/li>\n\n\n\n<li>Maximum 10 slides can be used (including 1 title, 8 content and 1 thank you slide). All figures,references should be incorporated in this limit. The submission should be done in pdf format only.<\/li>\n\n\n\n<li>Presentation should clearly state the problem statement\/novel ideas, proposed solution (results, and applications) of the contribution, silicon results if relevant\/available.<\/li>\n\n\n\n<li>Use speaker notes to provide more details to the reviewer wherever necessary.<\/li>\n\n\n\n<li>Presentation exceeding the page limit or identifying the authors\/organization will be rejected without review.<\/li>\n\n\n\n<li>Submissions will undergo a double-blind review.<\/li>\n\n\n\n<li class=\"justifyText\">For selected presentation, authors need to submit recorded video of the presentation. Further details will be shared with the selected authors after acceptance notification.<\/li>\n<\/ul>\n\n\n\n<p><\/p>\n\n\n\n<div class=\"wp-block-buttons has-custom-font-size has-medium-font-size is-content-justification-center is-layout-flex wp-container-22\">\n<div class=\"wp-block-button is-style-fill\"><a class=\"wp-block-button__link has-high-flight-gradient-background has-background wp-element-button\" href=\"https:\/\/vlsid.org\/wp-content\/uploads\/2023\/09\/Call-for-User-Design-Track-Submission_Updated_090623_v1.1.pdf\" style=\"border-radius:20px\" target=\"_blank\" rel=\"noreferrer noopener\">Download UDT Flyer<\/a><\/div>\n\n\n\n<div class=\"wp-block-button\"><a class=\"wp-block-button__link has-high-flight-gradient-background has-background wp-element-button\" href=\"https:\/\/vlsid.org\/wp-content\/uploads\/2023\/09\/VLSID2024-User-Design-Track-Template_ver2.pptx\" style=\"border-radius:20px\" target=\"_blank\" rel=\"noreferrer noopener\">Download UDT Template<\/a><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Important Dates User Design Track No. Title of the Submission Name 1 A&nbsp;&nbsp;&nbsp;4Ghz SRAM in 3nm with novel DFT scheme to improve at speed fault coverage Sriharsha Enjapuri, Manish Trivedi, Deepesh Gujjar, Jaswinder Singh, Sandipan Sinha and Ramesh Halli 2 ATE&nbsp;&nbsp;&nbsp;Testing for Complex Memory at 7nm &#8211; DFT insights covering Peak-Power, Testing&nbsp;&nbsp;&nbsp;&amp; Issues Jaykumar&nbsp;&nbsp;&nbsp;Goraseeya and Raj Gandhi 3 TinyML&nbsp;&nbsp;&nbsp;System for Detecting Life-Threatening Ventricular Arrhythmias Vipin&nbsp;&nbsp;&nbsp;Gautam, Sharad Sinha and Shitala Prasad 4 Modulating&nbsp;&nbsp;&nbsp;Free Layer of Magnetic Tunnel Junction : A Novel Approach for&nbsp;&nbsp;&nbsp;Energy-Efficient Computing in Memory Alisha B , Dr. Tripti S. Warrier 5 Robust&nbsp;&nbsp;&nbsp;Noise Immune Inverting Schmitt Trigger for Radiation\u2026<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"blocksy_meta":{"styles_descriptor":{"styles":{"desktop":"","tablet":"","mobile":""},"google_fonts":[],"version":5}},"_links":{"self":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1561"}],"collection":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/comments?post=1561"}],"version-history":[{"count":83,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1561\/revisions"}],"predecessor-version":[{"id":3770,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1561\/revisions\/3770"}],"wp:attachment":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/media?parent=1561"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}