{"id":1948,"date":"2023-09-21T16:09:29","date_gmt":"2023-09-21T16:09:29","guid":{"rendered":"https:\/\/vlsid.org\/?page_id=1948"},"modified":"2024-01-06T07:24:44","modified_gmt":"2024-01-06T07:24:44","slug":"tutorial-schedule","status":"publish","type":"page","link":"https:\/\/vlsid.org\/tutorial-schedule\/","title":{"rendered":"Tutorial Schedule"},"content":{"rendered":"\n<div class=\"wp-block-getwid-section alignwide alignwide has-inner-blocks-gap-none getwid-margin-top-none getwid-margin-bottom-none\"><div class=\"wp-block-getwid-section__wrapper getwid-padding-top-none getwid-padding-bottom-none getwid-padding-left-none getwid-padding-right-none getwid-margin-left-none getwid-margin-right-none\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<h4 class=\"wp-block-heading has-text-align-center has-white-color has-mind-crawl-gradient-background has-text-color has-background\">Tutorial Venue&nbsp;&#8211;&nbsp;ITC Sonar<\/h4>\n<\/div><\/div><\/div><\/div><\/div>\n\n\n\n<h3 class=\"wp-block-heading has-text-align-center\">VLSID Tutorial Schedule (6-7th January 2024)<\/h3>\n\n\n\n<div class=\"wp-block-getwid-section alignfull alignfull\"><div class=\"wp-block-getwid-section__wrapper getwid-reset-min-height-tablet getwid-reset-min-height-mobile\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<\/style>\n<H5>Tutorial Day &#8211; 1 | 6<sup>th<\/sup> January 2024 | Saturday<\/h5> \n<div style=\"overflow-x: auto;\">\n<style type=\"text\/css\">\n\n.tg  {border-collapse:collapse;border-spacing:0;margin:0px auto;}\n.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-k4xf{background-color:#efefef;border-color:#000000;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-65px{background-color:#ecf4ff;border-color:#000000;text-align:left;vertical-align:top}\n.tg .tg-fm1b{background-color:#efefef;border-color:#000000;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-nif5{background-color:#00a046;border-color:#000000;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-rx3n{background-color:#680100;border-color:#000000;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-khcy{background-color:#34696d;border-color:#000000;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-rrsm{background-color:#154360;border-color:#000000;color:#ffffff;font-weight:bold;position:-webkit-sticky;position:sticky;\n  text-align:center;top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-oodr{background-color:#003532;border-color:#000000;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-tqgz{background-color:#ffffc7;border-color:#000000;text-align:left;vertical-align:top}\n.tg .tg-gn3e{background-color:#efefef;border-color:#000000;color:#343434;font-weight:bold;text-align:center;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-rrsm\" width=\"6%\">Start<\/th>\n    <th class=\"tg-rrsm\" width=\"6%\">End<\/th>\n    <th class=\"tg-rrsm\" width=\"8%\">Duration<\/th>\n    <th class=\"tg-rrsm\" colspan=\"4\">6th   Jan 2024<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-fm1b\">8:00 AM<\/td>\n    <td class=\"tg-fm1b\">9:30 AM<\/td>\n    <td class=\"tg-fm1b\">1:30<\/td>\n    <td class=\"tg-nif5\" colspan=\"4\">Registration<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-fm1b\"> <\/td>\n    <td class=\"tg-fm1b\"> <\/td>\n    <td class=\"tg-fm1b\"> <\/td>\n    <td class=\"tg-oodr\" width=\"20%\">Pala-1<\/td>\n    <td class=\"tg-oodr\" width=\"20%\">Pala-2<\/td>\n    <td class=\"tg-oodr\" width=\"20%\">Pala-3<\/td>\n    <td class=\"tg-oodr\" width=\"20%\">Pala-4<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-k4xf\"> <\/td>\n    <td class=\"tg-k4xf\"> <\/td>\n    <td class=\"tg-k4xf\"> <\/td>\n    <td class=\"tg-khcy\"><span style=\"font-weight:bold\">Session Chair: Prof. Virendra Singh, IIT Bombay<\/span><\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof. Suchismita Roy, NIT DGP <\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof. Ujjwal Guin, Auburn University, USA<\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof. Susmita Sur-Kolay, ISI <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-fm1b\">9:30 AM<\/td>\n    <td class=\"tg-fm1b\">12:30 PM<\/td>\n    <td class=\"tg-fm1b\">3:00<\/td>\n    <td class=\"tg-tqgz\"><a href=\"https:\/\/vlsid.org\/tutorial-1\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Recent   Advances in Test: Cell Aware and Timing Aware Fault Models, and Component   System Level Tests<br>     <br><span style=\"font-weight:bold\">Speaker: <\/span>Prof. Adit D. Singh, Godbold Endowed Chair Professor, Auburn   University, USA<\/a><\/td>\n    <td class=\"tg-65px\"><a href=\"https:\/\/vlsid.org\/tutorial-2-6th-jan-930-am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Digital   Design Verification &#8211; Objectives, Practices and Advanced Trends <br>     <br>     <br><span style=\"font-weight:bold\"> Speakers:<\/span> Karthik Rajakumar, Naveen Kothuri, Bhavya Sri Dasari and Pooja   Madhusoodhanan, Texas Instruments, Bangalore<\/a><\/td>\n    <td class=\"tg-tqgz\"><a href=\"https:\/\/vlsid.org\/tutorial-2-6th-jan-930-am-1230pm-ist-2\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Comprehensive   Guide to Navigating the Analog Design Landscape: From PDK Foundations to   Layout Optimization with Capless LDO and 10-bits SAR ADC Case Studies<br>     <br><span style=\"font-weight:bold\">Speakers:<\/span> Arnab Deb and Shramona Roy, CDAC, Bangalore<\/a><\/td>\n    <td class=\"tg-65px\"><a href=\"https:\/\/vlsid.org\/tutorial-4-6th-jan-930-am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Agile   Software-Hardware Co-Design of AI-Centric Heterogeneous SoCs <br>        <br> <span style=\"font-weight:bold\">Speaker:<\/span> Dr. Pradip Bose, Thomas J. Watson Research Center, IBM, USA<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-fm1b\">12:30 PM<\/td>\n    <td class=\"tg-fm1b\">1:30 PM<\/td>\n    <td class=\"tg-fm1b\">1:00<\/td>\n    <td class=\"tg-rx3n\" colspan=\"4\">Lunch<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-gn3e\"> <\/td>\n    <td class=\"tg-gn3e\"> <\/td>\n    <td class=\"tg-gn3e\"> <\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof.   Ansuman Banerjee, ISI<\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof.   Prajit Nandi, IIT KGP<\/td>\n    <td class=\"tg-khcy\">Session Chair: Preet Yadav, NXP &#038; Prof. Bhargab B. Bhattacharya, ISI<\/td>\n    <td class=\"tg-khcy\">Session Chair: Prof. Soumya Pandit, University of Calcutta<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-fm1b\" rowspan=\"2\">2:00 PM<\/td>\n    <td class=\"tg-fm1b\" rowspan=\"2\">5:00 PM<\/td>\n    <td class=\"tg-fm1b\" rowspan=\"2\">3:00<\/td>\n    <td class=\"tg-tqgz\" rowspan=\"2\">  <a href=\"https:\/\/vlsid.org\/tutorial-5-6th-jan-930-am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\">   <br><span style=\"font-weight:bold\">Title: <\/span> The Art of Chip Verification <br>     <br><span style=\"font-weight:bold\">Speakers:<\/span> Sivakumar P R and Satish Putta, Maven Silicon, Bangalore<\/a><\/td>\n    <td class=\"tg-65px\" rowspan=\"2\">   <a href=\"https:\/\/vlsid.org\/tutorial-6-6th-jan-1400-pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\">  <br><span style=\"font-weight:bold\">Title: <\/span>Evolution and Impact of Analog\/Mixed Signal Design from sub-micron to   sub-Angstrom CMOS technology over 3 decades<br>     <br> <span style=\"font-weight:bold\">Speaker:<\/span> Mrinal Das, Head, Global R&amp;D , Hardware Design Group, Synopsys<\/a><\/td>\n    <td class=\"tg-tqgz\"><a href=\"https:\/\/vlsid.org\/tutorial-7-6th-jan-1400-pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>EM\/Power   Side-Channel Analysis: Advanced ML attacks and Low-overhead Countermeasures   <br>     <br> <span style=\"font-weight:bold\">Speaker:<\/span> Prof. Debayan Das, Department of Electronic Systems Engineering, Indian   Institute of Science, Bangalore.<\/a><\/td>\n    <td class=\"tg-65px\" rowspan=\"2\"><a href=\"https:\/\/vlsid.org\/tutorial-8-6th-jan-1400-pm-1700pm-ist-2\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Digital and Analog\/Mixed-Signal ASIC Design Flow with SCL 180nm PDK <br>           <br>     <br><span style=\"font-weight:bold\">Speakers:<\/span> Venkata Reddy Kolagatla, Shramona Roy and Vivian Desalphine,   CDAC, Bangalore<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-tqgz\"><a href=\"https:\/\/vlsid.org\/tutorial-8-6th-jan-1400-pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Machine Learning for Design Automation of   Microfluidic Biochips: Current Status and Scope <br>     <br> <span style=\"font-weight:bold\">Speaker:<\/span> Prof. Sudip Roy, Indian Institute of Technology, Roorkee, India<\/a><\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n<\/div>\n\n<H5>Tutorial Day &#8211; 2 | 7<sup>th<\/sup> January 2024 | Sunday<\/h5>\n<div style=\"overflow-x: auto;\">\n\n<style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-spacing:0;margin:0px auto;}\n.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-jpa8{background-color:#00a046;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-baqh{text-align:center;vertical-align:top}\n.tg .tg-zdbk{background-color:#003532;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-9c27{background-color:#154360;color:#ffffff;font-weight:bold;position:-webkit-sticky;position:sticky;text-align:center;\n  top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-fuer{background-color:#34696d;color:#ffffff;font-weight:bold;text-align:left;vertical-align:top}\n.tg .tg-m9r4{background-color:#ffffc7;text-align:left;vertical-align:top}\n.tg .tg-0qe0{background-color:#ecf4ff;text-align:left;vertical-align:top}\n.tg .tg-4k42{background-color:#680100;color:#ffffff;font-weight:bold;text-align:center;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-9c27\" Width=\"6%\">Start<\/th>\n    <th class=\"tg-9c27\" Width=\"6%\">End<\/th>\n    <th class=\"tg-9c27\" Width=\"8%\">Duration<\/th>\n    <th class=\"tg-9c27\" colspan=\"4\">7th   Jan 2024<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-baqh\">8:00 AM<\/td>\n    <td class=\"tg-baqh\">9:30 AM<\/td>\n    <td class=\"tg-baqh\">1:30<\/td>\n    <td class=\"tg-jpa8\" colspan=\"4\">Registration<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-zdbk\" Width=\"20%\">Pala-1<\/td>\n    <td class=\"tg-zdbk\" Width=\"20%\">Pala-2<\/td>\n    <td class=\"tg-zdbk\" Width=\"20%\">Pala-3<\/td>\n    <td class=\"tg-zdbk\" Width=\"20%\">Pala-4<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-fuer\"> <span style=\"font-weight:bold\">Session Chair: <\/span>Prof. Indranil Sengupta, IIT KGP<\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair: <\/span>Prof. Mousumi Basu, IIEST  <\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair: <\/span>Prof. Debashis De, MAKAUT<\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair:<\/span> Prof. Manan Suri, IIT Delhi<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">9:30 AM<\/td>\n    <td class=\"tg-baqh\">12:30 PM<\/td>\n    <td class=\"tg-baqh\">3:00<\/td>\n    <td class=\"tg-m9r4\"><a href=\"https:\/\/vlsid.org\/tutorial-10-7th-jan-930am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Design Automation for Quantum   Computing<br>     <br>     <span style=\"font-weight:bold\"> Speakers:<\/span> Prof. Prabhat Mishra, University of Florida, Gainesville,   Florida, USA and Prof. Robert Wille, Technical University of Munich, Germany<\/a><\/td>\n    <td class=\"tg-0qe0\"><a href=\"https:\/\/vlsid.org\/tutorial-11-7th-jan-930am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> VLSI Sensors, Circuits, and   Systems for Particle Physics Experiments <br>     <br>     <br> <span style=\"font-weight:bold\">Speaker:<\/span> Prof.   Soumyajit Mandal, Brookhaven National Laboratory, Upton, USA<\/a><\/td>\n    <td class=\"tg-m9r4\"><a href=\"https:\/\/vlsid.org\/tutorial-11\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Security of Emergent   Autonomous Vehicles: From Sensors to Systems <br>     <br>     <br><span style=\"font-weight:bold\">Speaker:<\/span> Prof. Sandip   Ray, University of Florida, Gainesville, USA<\/a><\/td>\n    <td class=\"tg-0qe0\"><a href=\"https:\/\/vlsid.org\/tutorial-12-7th-jan-930am-1230pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Neuromorphic Systems: From   Event-driven sensors to In-Memory Computing Circuits<br>     <br>      Speaker: Prof. Arindam Basu, University of Hong Kong<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">12:30 PM<\/td>\n    <td class=\"tg-baqh\">1:30 PM<\/td>\n    <td class=\"tg-baqh\">1:00<\/td>\n    <td class=\"tg-4k42\" colspan=\"4\">Lunch<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-baqh\"> <\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair:<\/span> Abhisek Nigam, HCLTech<\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair: <\/span>Prof.   Ujjwal Maulik, JU<\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair:<\/span> Prof. Soumyajit Dey, IIT KGP<\/td>\n    <td class=\"tg-fuer\"><span style=\"font-weight:bold\">Session Chair: <\/span> Dr. Kamalika Datta, DFKI Bremen \n&#038; Prof. Pritha Banerjee, CU<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\" rowspan=\"2\">2:00 PM<\/td>\n    <td class=\"tg-baqh\" rowspan=\"2\">5:00 PM<\/td>\n    <td class=\"tg-baqh\" rowspan=\"2\">3:00<\/td>\n    <td class=\"tg-m9r4\" rowspan=\"2\"><a href=\"https:\/\/vlsid.org\/tutorial-14-7th-jan-1400pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Designing Efficient and Secure NoC-based Heterogeneous SoCs   <br>     <br> <span style=\"font-weight:bold\">Speakers:<\/span> Prof. Sujay Deb, Professor, IIIT Delhi,  Subhra Kanti Das, Head, Research and Technology,   Thales, India,  Mitali Sinha, Researcher, Shell   India Markets Private Limited, Bangalore and Sidharatha Sankar Rout,   Technical Leader, STMicroelectronics, Noida<\/a><\/td>\n    <td class=\"tg-0qe0\" rowspan=\"2\"><a href=\"https:\/\/vlsid.org\/tutorial-15-7th-jan-1400pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title: <\/span>Design Methods and Tools for Future-Generation Computer   Architectures <br>     <br> <span style=\"font-weight:bold\">Speakers:<\/span> Prof. Farhad Merchant, Newcastle University, UK, Prof. Rolf Drechsler, University   of Bremen, Germany and Vikas Rana<\/a><\/td>\n    <td class=\"tg-m9r4\" rowspan=\"2\"><a href=\"https:\/\/vlsid.org\/tutorial-16-7th-jan-1400pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Cerifiable Autonomous Cyber-Physical System Design <br>     <br>     <br> <span style=\"font-weight:bold\">Speakers:<\/span> Prof. Samarjit Chakrabarty, UNCChapel Hill; Prof. Sridhar Duggirala, UNC Chapel   Hill and Prof. Indranil Saha, IIT Kanpur<\/a><\/td>\n    <td class=\"tg-0qe0\"><a href=\"https:\/\/vlsid.org\/tutorial-17-7th-jan-1400pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> In-Memory Computing for   Robust and Efficient AI: Opportunities and Challenges <br>     <br> <span style=\"font-weight:bold\">Speakers:<\/span> Prof. Priyadarshini Panda and Prof. Abhishek Moitra, Yale University<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-0qe0\"><a href=\"https:\/\/vlsid.org\/tutorial-18-7th-jan-1400pm-1700pm-ist\/\" target=\"_blank\" style=\"text-decoration:none; color:#3a4f66;\" rel=\"noopener\"><span style=\"font-weight:bold\">Title:<\/span> Semiconductor Lithography and Process Scaling   Methods from 65 nm to 2 nm <br>     <br> <span style=\"font-weight:bold\">Speakers:<\/span> Sachin Shrivastava   and Vishal Rastogi, Cadence Design Systems, Bangalore<\/a><\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"<p>VLSID Tutorial Schedule (6-7th January 2024)<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"blocksy_meta":{"styles_descriptor":{"styles":{"desktop":"","tablet":"","mobile":""},"google_fonts":[],"version":5}},"_links":{"self":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1948"}],"collection":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/comments?post=1948"}],"version-history":[{"count":190,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1948\/revisions"}],"predecessor-version":[{"id":4974,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/1948\/revisions\/4974"}],"wp:attachment":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/media?parent=1948"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}