{"id":2762,"date":"2023-12-02T08:20:50","date_gmt":"2023-12-02T08:20:50","guid":{"rendered":"https:\/\/vlsid.org\/?page_id=2762"},"modified":"2024-01-08T04:22:55","modified_gmt":"2024-01-08T04:22:55","slug":"confernce-detailed-schedule","status":"publish","type":"page","link":"https:\/\/vlsid.org\/confernce-detailed-schedule\/","title":{"rendered":"Conference  Detailed Schedule"},"content":{"rendered":"\n<div class=\"wp-block-getwid-section alignfull alignfull getwid-section-content-full-width\"><div class=\"wp-block-getwid-section__wrapper\" style=\"padding-left:6px;padding-right:0px\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<div class=\"wp-block-getwid-tabs button_tab has-layout-horizontal-center\" data-active-tab=\"0\"><ul class=\"wp-block-getwid-tabs__nav-links\"><\/ul>\n<div class=\"wp-block-getwid-tabs__nav-link\"><h6 class=\"wp-block-getwid-tabs__title-wrapper\"><a href=\"#\"><span class=\"wp-block-getwid-tabs__title\">8th Jan<\/span><\/a><\/h6><\/div><div class=\"wp-block-getwid-tabs__tab-content-wrapper\"><div class=\"wp-block-getwid-tabs__tab-content\">\n<style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-spacing:0;margin:0px auto;}\n.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-p1xr{background-color:#34696D;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-ir36{background-color:#009901;color:#FFF;font-weight:bold;text-align:center;vertical-align:middle}\n.tg .tg-0nyp{background-color:#999903;color:#FFF;text-align:center;vertical-align:middle}\n.tg .tg-puht{background-color:#68CBD0;color:#343434;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-7geq{background-color:#ffffc7;text-align:center;vertical-align:top}\n.tg .tg-29iq{background-color:#FFFFC7;text-align:center;vertical-align:top}\n.tg .tg-eyg1{background-color:#FFFFC7;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-etrd{background-color:#656565;color:#FFF;text-align:center;vertical-align:top}\n.tg .tg-bcs8{background-color:#FFC702;color:#343434;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-1uj8{background-color:#34696D;color:#FFF;font-weight:bold;position:-webkit-sticky;position:sticky;text-align:center;\n  top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-nrix{text-align:center;vertical-align:middle}\n.tg .tg-amwm{font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-kxn2{background-color:#EFEFEF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-0r9i{background-color:#ECF4FF;text-align:center;vertical-align:top}\n.tg .tg-o2c7{background-color:#ECF4FF;font-weight:bold;text-align:center;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-1uj8\">Start<\/th>\n    <th class=\"tg-1uj8\">End<\/th>\n    <th class=\"tg-1uj8\">Duration<\/th>\n    <th class=\"tg-1uj8\" colspan=\"6\">8th   Jan 2024<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-nrix\">8:00 AM<\/td>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-ir36\" colspan=\"6\">Registration<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-amwm\" colspan=\"6\">Plenary Room<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">10:00 AM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-kxn2\" colspan=\"6\">Inauguration Ceremony<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:00 AM<\/td>\n    <td class=\"tg-nrix\">10:25 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-bcs8\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br> Tittle: Pushing New Frontiers of Compute and Data Connectivity -The Rise of Custom Silicon and Chiplets in the AI era<br>Sudhir Mallya,   SVP Corporate Marketing, Alphawave Semi <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:25 AM<\/td>\n    <td class=\"tg-nrix\">10:50 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-puht\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: Innovations Driving Next Generation Accelerated Data Infrastructure<br>Sandeep Bharathi, Chief Development   Officer, Marvell<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:50 AM<\/td>\n    <td class=\"tg-nrix\">11:15 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-bcs8\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: Gen-erational Transformations in VLSI Engineering <br>Aman Joshi, Vice President, Design   Enablement &amp; Automation, Western Digital<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:15 AM<\/td>\n    <td class=\"tg-nrix\">11:55 AM<\/td>\n    <td class=\"tg-nrix\">00:40<\/td>\n    <td class=\"tg-0nyp\" colspan=\"6\">Tea Break and Inauguration of Exhibit Area<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" colspan=\"3\" rowspan=\"3\">   <br>  <br>    <br>  <br>  &nbsp;&nbsp;<br>&nbsp;&nbsp;<br>&nbsp;&nbsp;<\/td>\n    <td class=\"tg-29iq\">Ballroom1<\/td>\n    <td class=\"tg-0r9i\">Ballroom2<\/td>\n    <td class=\"tg-29iq\">Ballroom3<\/td>\n    <td class=\"tg-0r9i\">Ballroom4<\/td>\n    <td class=\"tg-29iq\">Ballroom5<\/td>\n    <td class=\"tg-0r9i\">Ballroom6<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-etrd\">Track1 &#8211; Technical Track<br>     EDA<\/td>\n    <td class=\"tg-etrd\">Track2   &#8211; Technical Track<br>     AMS<\/td>\n    <td class=\"tg-etrd\">Track3 &#8211; Industry   Forum<\/td>\n    <td class=\"tg-etrd\">Track4   &#8211; Technical Track<br>     Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS)   Design<\/td>\n    <td class=\"tg-etrd\">Track5 &#8211; User Design   Track<\/td>\n    <td class=\"tg-etrd\">Track6   &#8211; Technical Track<br>     Test, Verification, and Reliability<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-p1xr\">Session Chair: Umesh Nair, AMD<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Baibhab Chatterje, UFL <\/td>\n    <td class=\"tg-p1xr\">Session Chair: Navin   Bishnoi, Marvell, India<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Arindam Basu, Univ Hong Kong<\/td>\n    <td class=\"tg-p1xr\">Session Chair:   Rituparna Mondal, MediaTek<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Tapan J   Chakraborty, CG<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:55 AM<\/td>\n    <td class=\"tg-nrix\">12:15 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 39<\/span>      <br>MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence   Strategy<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Sashank   Nishad (IntelTechnologyIndiaPvtLtd); Santanu Kundu (Intel Technology India   Pvt. Ltd.); Nicolas Richaud (Intel Corporation); Mallikarjun S   (IntelTechnologyIndiaPvtLtd); Manoranjan Prasad (IntelTechnologyIndiaPvtLtd);   Lennart Renker (Intel Corporation)<\/td>\n    <td class=\"tg-0r9i\">Luminary Talk   (Invited):<br> Analog Design in VLSI: Blurring Boundaries in the Emerging   Technology World<br>     <br>Prof. Prajit Nandi, IIT KGP<\/td>\n    <td class=\"tg-29iq\"> Leapfrogging into next decade of silicon to system <br> <br>Raghu Panicker, Kaynes<\/td>\n    <td class=\"tg-0r9i\">Luminary Talk (Invited):   <br>Efficient AI Algorithm and Hardware Design with Neuromorphic Computing<br>     <br>     <br>Prof. Priyadarshini Panda, Yale U<\/td>\n    <td class=\"tg-7geq\" rowspan=\"5\"><span style=\"font-weight:bold\">UDT Paper ID : 8<\/span><br><span style=\"color:#222\">A 4Ghz SRAM in 3nm with novel DFT scheme to improve at speed fault coverage.<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Sriharsha Enjapuri, Manish Trivedi, Deepesh Gujjar, Jaswinder Singh, Sandipan Sinha and Ramesh Halli<\/span><br><span style=\"color:#222\">(MediaTek India Technology Pvt. Ltd)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 21<\/span><br><span style=\"color:#222\">FastMiner-Design and Implementation of FPGA accelerated Bitcoin Miner<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Mayank Kabra, Harshita Gupta, Asmita Zjigyasu and Madhav Rao (<\/span>International Institute of Information Technology Bangalore)<br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 25<\/span><br><span style=\"color:#222\">Process Mismatch Tolerant Adaptive Read Assist for SRAM using Replica Bias Control<\/span><br>Authors :<br><span style=\"color:#222\">Ashish Kumar (STMicroelectronics India Pvt. Limited)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 43<\/span><br><span style=\"color:#222\">Approximate CNN for Edge Computing<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Abhinav K, Nalesh S and Kala S <\/span><br><span style=\"color:#222\">(Indian Institute of Information Technology Kottayam, Kerala and Cochin University of Science and Technology, Kochi, Kerala)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 46<\/span><br><span style=\"color:#222\">ATE Testing for Complex Memory at 7nm &#8211; DFT insights covering Peak-Power, Testing &amp; Issues<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Jaykumar Goraseeya and Raj Gandhi (E Infochips Pvt. Ltd)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 51<\/span><br><span style=\"color:#222\">System-Level Modeling for Real-Time DNN Inference on Edge Devices<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Tom Jose and Deepak Shankar (Mirabilis Design)<\/span><\/td>\n    <td class=\"tg-0r9i\">Luminary Talk   (Invited): <br>Energy Efficient Architectures <br> <br> Prof. Virendra Singh, IIT Bombay<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:15 PM<\/td>\n    <td class=\"tg-nrix\">12:35 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 40  <\/span>    <br>Unlocking the Power of Machine Learning for Faster PCB Package and Board   PDN Convergence <br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Manoranjan   Prasad (Intel Technology India Pvt Ltd); Santanu Kundu (Intel Technology   India Pvt. Ltd.); Lennart Renker (Intel Deutschland GmbH); Rakesh Ranjan   (Intel Technology India Pvt Ltd)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 34 <\/span> <br>Use of current-mode and voltage-mode receivers together for on-chip   multipoint-to-multipoint data transmission across global interconnects <br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Jahnvi Singh   (IIT Kharagpur); Nijwm Wary (IIT Bhubaneswar); Pradip Mandal (IIT Kharagpur)<\/td>\n    <td class=\"tg-29iq\">Research Driven Hardware Security \u2013 Landscape, Ecosystem and Opportunities <br><br><br>  Teja Chintalapati, DSCI<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID:  38  <\/span>  <br>Authenticating Edge Neural Network through Hardware Security Modules and   Quantum-Safe Key Management<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Swathi   KumarVembu (NTU); Anupam Chattopadhyay (Nanyang Technological University);   Sayandeep Saha (Indian Institute of Technology, Kharagpur)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 56 <\/span>   <br>Optimizing Task Scheduling in Multi-thread Real-Time Systems using   Augmented Particle Swarm Optimization<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>B Naresh   Kumar Reddy (NIT Tiruchirappalli); Yellapradaga Charan Krishna (Amrita Vishwa   Vidyapeetham, Chennai); Poosarla Naga Satya Nitish (Amrita Vishwa   Vidyapeetham, Chennai); Sita Devi Bharatula (Amrita Vishwa Vidyapeetham,   Chennai)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:35 PM<\/td>\n    <td class=\"tg-nrix\">12:55 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 175 <\/span>     <br>Artificial Neural Network-based Prediction and Alleviation of Congestion   during Placement <br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Pooja   Beniwal (Indraprastha Institute of Information Technology Delhi   (IIIT-Delhi)); Sneh Saurabh (Indraprastha Institute of Information   Technology)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 77   <\/span>   <br>A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for   Ultra-Low Power IoT Applications<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br> Chetan   Mittal (International institute of information technology Hyderabad); Arnab   Dey (IIITHyderabad); Anubhab Banerjee (International Institute of Information   Technology,Hyderabad,India); Ashfakh Huluvallay (IIIT Hyderabad); Zia Abbas   (International Institute of Information Technology (IIIT), Hyderabad)<\/td>\n    <td class=\"tg-29iq\">Transforming   semiconductor design using shift-left methodologies<br>     <br>Umesh Sisodia, President &amp; CEO, CircuitSutra<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID:  68 <\/span>  <br>Long Short-Term Memory (LSTM)-based Cuffless Continuous Blood Pressure   Monitoring<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Vijay Kumar   (Indian Institute of Technology Delhi); Goldy Goldy (IIT Delhi); Kolin Paul   (IIT Delhi); Mahesh Chowdhary (ST Microelectronics)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 61 <\/span>   <br>Fault-Tolerant Floating-Point Multiplier Design for Mission Critical   Systems<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Raghavendra   Kumar Sakali (IIITDM Kancheepuram); Sreehari Veeramachaneni (GRIET,   Hyderabad); Noor Mahammad Sk (Indian Institute of Information Technology   Design and Manufacturing (IIITDM) Kancheepuram)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:55 PM<\/td>\n    <td class=\"tg-nrix\">1:15 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 286<\/span><br>A Dynamic Programming Based Graph Traversal Approach for Efficient   Implementation of Nearest Neighbor Architecture in 2D <br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Sneha Lahiri   (Dr. B. C. Roy Engineering College, Durgapur); Megha Kesh (Dr. B. C. Roy   Engineering College, Durgapur); Rupsa Mandal (Dr. B. C. Roy Engineering   College, Durgapur); Sovan Bhattacharya (Assistant Professor, Dr. B. C. Roy   Engineering College, Durgapur); Anirban Bhattacharjee (KIT); Dola Sinha (Dr.   B. C. Roy Engineering College, Durgapur); Chandan Bandyopadhyay (Dr. B. C.   Roy Engineering College, Durgapur); Hafizur Rahaman (IIEST, Shibpur); Rolf   Drechsler (university of bremen); Robert Wille (university of bremen)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 80 <\/span>    <br>A 3nm Ultra-High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range   <br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Sandipan   Sinha (Mediatek Bangalore Pvt. Ltd.); Manish Trivedi (Mediatek Bangalore PVT   LTD); Jaswinder Singh (Mediatek Bangalore PVT LTD); Sriharsha Enjapuri   (Mediatek Bangalore PVT LTD); Deepesh Gujjar (Mediatek Bangalore PVT LTD);   Ramesh Halli (Mediatek Bangalore PVT LTD); GiriShankar Gurumurthy (Mediatek   Bangalore PVT LTD)<br>     <\/td>\n    <td class=\"tg-29iq\">Sustainable VLSI   Designing: Innovations and Commitment<br>     <br>Abhijith M V, Manager Application Engineering, Ansys<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID:  217 <\/span>    <br>MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA   Architectures<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Prakhar   Diwan (Indian Institute of Technology Bombay); Suryakant Toraskar (Indian   Institute of Technology Bombay); Varun Venkitaraman (Indian Institute of   Technology Bombay); Nirmal Kumar Boran (National Institute of Technology   Calicut); Chandramani Chaudhary (National Institute of Technology Calicut);   Virendra Singh (Indian Institute of Technology Bombay)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 124 <\/span>   <br>LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error   in Multicore<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Avishek   Choudhury (New Alipore College, University of Calcutta); Brototi Mondal   (Sammilani Mahavidyalaya); Kolin Paul (IIT Delhi); Biplab K. Sikdar (IIEST   Shibpur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">1:15 PM<\/td>\n    <td class=\"tg-nrix\">1:35 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 436  <\/span>    <br>A method to accurately simulate and detect transition time instants in   piecewise linear SMPS circuits <br>     <br><span style=\"font-weight:bold\">Author:<\/span> <br>Saloni Tandon   (Cadence Design Systems)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 88 <\/span><br>Phase frequency detector with zero-reset pulse   for low-spur Phase-locked loop applications<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Marichamy   Divya (Department of Micro and Nanoelectronics, Vellore Institute of   Technology); Siva Kumar Rapina (MSDG, Microchip Technology); Kumaravel S   (Department of Micro and Nanoelectronics, Vellore Institute of   Technology)<br>     <\/td>\n    <td class=\"tg-29iq\">Unlocking the   Edge AI Potential: Development, Applications, and Lifecycle Management<br>     <br>Sindhu Ramachandran, Director &#8211; Technology, CoE Leader for Artificial   Intelligence, Quest Global<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper Id: 170<\/span><br> CAD Tools Pathway in Hardware Security<br><br>  <span style=\"font-weight:bold\">Author:<\/span> Sree Ranjani Rajendran (University of Florida); Farimah Farahmandi   (University of Florida); Mark Tehranipoor (University of Florida)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 149  <\/span>   <br>An Amalgamated Testability Measure Derived from Machine Intelligence<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Soham Roy   (Intel Corporation); Vishwani Agrawal (Auburn University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">1:35 PM<\/td>\n    <td class=\"tg-nrix\">2:35 PM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-0nyp\" colspan=\"6\">Lunch<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:35 PM<\/td>\n    <td class=\"tg-nrix\">3:00 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-bcs8\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span> <br> Title: Design and Analysis of Multi-Die and 3D-IC Systems.<br>Dr. Prith Banerjee, CTO, Ansys, USA<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:00 PM<\/td>\n    <td class=\"tg-nrix\">3:25 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-puht\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span> <br>Title: Rethinking computing with Neuro-inspired Learning: Algorithms and Hardware Architecture<br>Prof. Kaushik Roy, Purdue University <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:25 PM<\/td>\n    <td class=\"tg-nrix\">3:50 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-bcs8\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: How RISCV is impacting the Embedded world!<br>Subhra Kanti Das, Head Research &amp;   Technology \u2013 Engineering Competence Centre, , Thales, India<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:50 PM<\/td>\n    <td class=\"tg-nrix\">4:15 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-puht\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: Microchip Technology Driving Market Trends and Skill Development Globally<br>Srikanth Settikere, Vice President and Managing Director, Microchip India Development Centers<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:15 PM<\/td>\n    <td class=\"tg-nrix\">4:55 PM<\/td>\n    <td class=\"tg-nrix\">00:40<\/td>\n    <td class=\"tg-0nyp\" colspan=\"6\">Tea Break <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-etrd\">Track7   &#8211; Technical Track<br>Emerging Computing and post-CMOS Technologies<\/td>\n    <td class=\"tg-etrd\">Track8   &#8211; Technical Track<br>     AMS<\/td>\n    <td class=\"tg-etrd\">Track9 &#8211; Industry   Forum<\/td>\n    <td class=\"tg-etrd\">Track10   &#8211; Technical Track<br>     Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS)   Design<\/td>\n    <td class=\"tg-etrd\">Track11 &#8211; User Design   Track<\/td>\n    <td class=\"tg-etrd\">Track12   &#8211; Technical Track<br>     Test, Verification, and Reliability<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"6%\"> <\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof. Bhargab B. Bhattacharya, ISI<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Maryam Shojaei Baghini, IIT Bombay<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Shiv Harit Mathur, Western Digital<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Dr.   Navneet Gupta, WDC<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Ayan   Dutta, WDC<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Debesh Das, JU<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:55 PM<\/td>\n    <td class=\"tg-nrix\">5:15 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 89 <\/span>   <br>Margin Propagation based Analog Soft-Gates for Probabilistic Computing   <br><br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ankita Nandi   (Indian Institute of Science (IISc)); Pratik Kumar (Indian Institute of   Science (IISc)); Shantanu Chakrabartty (Washington University in St. Louis);   Chetan Singh Thakur (Indian Institute of Science (IISc))<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 94 <\/span>    <br>An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in   FMCW Radar Synthesizers.<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Sumit Kumar   (Indian Institute of Science); Dr. Gaurab Banerjee (Indian Institute of   Science Bangalore)<\/td>\n    <td class=\"tg-29iq\">Indigenization   of Next Generation Electronic System Design using High Performance and   Adaptive Computing<br>     <br>Rohith Gopalakrishna, Country Sales Manager, AMD<\/td>\n    <td class=\"tg-0r9i\">Luminary   Talk (Invited): <br>Computing-In-Memory for Edge Devices: Beyond DNN Acceleration <br> <br> Prof. Saibal Mukhopadhyay, Georgia Tech<br>     <\/td>\n    <td class=\"tg-7geq\" rowspan=\"5\"><span style=\"font-weight:bold\">UDT Paper ID : 37<\/span><br><span style=\"color:#222\">Low-cost, Power IR drop consideration methodology for high contact resistance in advanced technologies nodes for robust memory design and accurate characterization.<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Praveen Kumar Verma, Anuj Dhillon, Harshit Sharma and Vartul Sharma (STMicroelectronics India Pvt. Limited)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 40<\/span><br><span style=\"color:#222\">CRVPGen : C-Random verification programs for Processor design validation<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Srinivasa Tipparaju, Rishna Patteri, Bijay Sharma and Karun Talari<\/span><span style=\"color:black\"> <\/span><span style=\"color:#222\">(MediaTek India Technology Pvt. Ltd)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 58<\/span><br><span style=\"color:#222\">TinyML System for Detecting Life-Threatening Ventricular Arrhythmias<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Vipin Gautam, Sharad Sinha and Shitala Prasad (Indian Institute of Technology, Goa)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 78<\/span><br><span style=\"color:#222\">SPARC &#8211; An intelligent autonomous flow for power switch Selection, Placement, Auto Routing and Connectivity optimization<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Subbash K P, Pardhu Pavan S and Vikash K T (Wester Digital)<\/span><span style=\"color:black\"> <\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 80<\/span><br><span style=\"color:#222\">Robust Noise Immune Inverting Schmitt Trigger for Radiation Exposed Environment<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Aryan Kannaujiya and Ambika Prasad Shah<\/span><br><span style=\"color:#222\">(Indian Institute of Technology Jammu)<\/span><br><br><br><span style=\"font-weight:bold\">UDT Paper ID : 83<\/span><br><span style=\"color:#222\">Modulating Free Layer of Magnetic Tunnel Junction : A Novel Approach for Energy-Efficient Computing in Memory<\/span><br><span style=\"font-weight:bold\">Authors :<\/span><br><span style=\"color:#222\">Alishaa B and Dr.Tripti S. Warrier  (<\/span>Cochin University of Science and Technology<span style=\"color:#222\">)<\/span> <br> <br> <br><span style=\"font-weight:bold\">UDT Paper ID : <\/span><br> Efficient   Workload Optimization for CPU-GPU Co-Design in Intelligent Cyber-Physical   Systems <br><br> <span style=\"font-weight:bold\">Authors :<\/span> <br>Ashiqur    Molla, Suraj Singh, Srijeeta Maity and Soumyajit Dey  <\/td>\n    <td class=\"tg-0r9i\">Luminary   Talk (Invited): <br>Reversible and Quantum Computing \u2013 Testability and Fault Tolerance Issues <br> <br> Prof. Indranil Sengupta, IIT KGP<br>     <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:15 PM<\/td>\n    <td class=\"tg-nrix\">5:35 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 183<\/span>      <br>Thermal Crosstalk Analysis in ReRAM Passive Crossbar Arrays <br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Shubham   Pande (IIT Madras); Bhaswar Chakrabarti (Indian Institute of Technology,   Madras); Anjan Chakravorty (Indian Institute of Technology, Madras)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 97<\/span>    <br>A sub-\u00b5W Fully Integrated Compact CMOS Temperature Sensor for Passive RFID   Applications<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Jayaram   chilaka (NITWarangal); Sreehari Rao Patri (NIT Warangal)<\/td>\n    <td class=\"tg-29iq\">Achieving   power efficiencies in GenAI era<br>     <br>Sumit Goswami, Senior Director Of Engineering, Qualcomm<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 283 <\/span>    <br>ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor   Embedded Systems<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Debabrata   Senapati (IIT Guwahati); Dharmendra Maurya (CSE, IIT Guwahati); Arnab Sarkar   (IIT Kharagpur); Chandan Karfa (Indian Institute of Technology Guwahati)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 185  <\/span>   <br>FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure   on Network-on-Chip Processors<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>N. Vamshi   Krishna (Birla Institute Of Technology &amp; Science &#8211; Pilani, Hyderabad   Campus); Anushka Chaudhary (Birla Institute Of Technology &amp; Science &#8211;   Pilani, Hyderabad Campus); Soumya J (Birla Institute Of Technology &amp;   Science &#8211; Pilani, Hyderabad Campus)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:35 PM<\/td>\n    <td class=\"tg-nrix\">5:55 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 213  <\/span>   <br>Optimized QAOA ansatz design for  two-body Hamiltonian problems <br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Ritajit   Majumdar (Indian Statistical Institute); Debasmita Bhoumik (Indian   Statistical Institute); Dhiraj Madan (IBM India Research Lab); Dhinakaran   Vinayagamurthy (IBM India Research Lab); Shesha S. Raghunathan (IBM India   Research Lab); Susmita SurKolay (INDIAN STATISTICAL INSTITUTE)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 99<\/span>    <br>A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar   Current Signals     <br><br><span style=\"font-weight:bold\">Authors: <\/span><br>Tamal   Chowdhury (Indian Institute of Technology, Kharagpur); Pradip Mandal (Indian   Institute of Technology, Kharagpur)<\/td>\n    <td class=\"tg-29iq\">Identifying   and Resolving multi-path Cyber-Physical System using a Reverse Engineering   Platform<br>     <br>Deepak Shankar, Vice President Technology, Mirabilis<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 321<\/span>    <br>Early Execution for Soft Error Detection<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Raj Kumar   Choudhary (Indian Institute of Technology Bombay); Janeel Patel (Indian   Institute of Technology Bombay); Virendra Singh (Indian Institute of   Technology Bombay)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID:207 <\/span>  <br> Near Threshold at Gate based Test for Stuck-on Fault in Scan-chain   Testing<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>R S   Haripriya (Indian Institute of Technology, Tirupati); Soumitro Vyapari   (Indian Institute of Technology, Tirupati); Jaynarayan Thakurdas Tudu (Indian   Institute of Technology, Tirupati)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:55 PM<\/td>\n    <td class=\"tg-nrix\">6:15 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 308 <\/span>    <br>Finding a Promising Oxide Material for Resistive Random Access Memory with   Graphene Electrode <br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Kanupriya   Varshney (IIT Ropar); Mani shankar Yadav (IIT Ropar); Devarshi Mrinal Das   (IIT Ropar); Brajesh Rawat (IIT Ropar)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 104 <\/span>   <br>A Compact Low-Power 29 Gb\/s Pseudo Random Quaternary Sequence   Generator<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ishan Mishra   (Indian Institute of Technology Bombay); Ganpat Anant Parulekar (Indian   Institute of Technology Bombay); Shalabh Gupta (IIT Bombay)<\/td>\n    <td class=\"tg-29iq\"> Integration in GaN: Challenges and Prospects &#8211; An Examination of Lateral Gallium Nitride (GaN) Power Devices After a Decade of Development <br><br>  Syed Asif Eqbal, Tagore   Tech<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID:  430<\/span>     <br>Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall   Detector Implementation On FPGA<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Tamonash   Bhattacharyya (Indian Institute of Engineering Science and   Technology,Shibpur); Prasun Ghosal (IIEST, Shibpur); SONAM SINGH   (Indraprastha Institute of Information Technology Delhi); Sujay Deb (IIIT   Delhi)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 327<\/span>   <br>X-Tolerant Logic BIST for Automotive Designs using Observation Scan   Technology<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br>Ashrith   Harith (Siemens DISW); Nilanjan Mukherjee (Siemens Digital Industries   Software); Yingdi Liu (Siemens Digital Industries Software); Jeffrey Mayer   (Siemens Digital Industries Software)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">6:15 PM<\/td>\n    <td class=\"tg-nrix\">6:35 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Paper ID: 358 <\/span>     <br>Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic   Biochips with Latches <br> <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Tamal Mandal   (IIT Roorkee, India); Debraj Kundu (IIT Roorkee); Sudip Roy (IIT Roorkee)<\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 403<\/span>    <br>Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF Energy   Harvester<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Sumit Saha   (Indian Institute of Technology Bombay); Prasad B Kanyaka (IIT Bombay); Mark   Last (Ohio State University); Nima Ghalichechian (Georgia Tech University);   V. Ramgopal Rao (IIT Bombay); Maryam Shojaei Baghini (Department of   Electrical Engg., IIT-Bombay)<\/td>\n    <td class=\"tg-29iq\">Neuromorphic   processors &#8211; Introducing the domain, the opportunities, the innovations<br> <br>Uma Mahesh, Co-Founder, Innatera Nanosystems<\/td>\n    <td class=\"tg-o2c7\"> <\/td>\n    <td class=\"tg-o2c7\"><span style=\"font-weight:bold\">Paper ID: 419 <\/span>    <br>Revisiting Test Compression Configuration in Context of Multi-Core Testing   Using Packetized Scan Network<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Subhadip   Kundu (Qualcomm); Jais Abraham (Qualcomm)<\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-tabs__nav-link\"><h6 class=\"wp-block-getwid-tabs__title-wrapper\"><a href=\"#\"><span class=\"wp-block-getwid-tabs__title\">9th Jan<\/span><\/a><\/h6><\/div><div class=\"wp-block-getwid-tabs__tab-content-wrapper\"><div class=\"wp-block-getwid-tabs__tab-content\">\n<style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-spacing:0;margin:0px auto;}\n.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-p1xr{background-color:#34696D;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-lk2o{background-color:#999903;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-kffi{background-color:#34696D;color:#FFF;text-align:center;vertical-align:top}\n.tg .tg-k4xr{background-color:#FFCCC9;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-e68y{background-color:#FFCB2F;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-gxkf{background-color:#999903;color:#FFF;text-align:center;vertical-align:top}\n.tg .tg-jaxz{background-color:#DAE8FC;text-align:center;vertical-align:middle}\n.tg .tg-29iq{background-color:#FFFFC7;text-align:center;vertical-align:top}\n.tg .tg-4ztr{background-color:#FFC702;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-k5c1{background-color:#ffffc7;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-eyg1{background-color:#FFFFC7;text-align:center;vertical-align:top}\n.tg .tg-ql2y{background-color:#FFC702;color:#013300;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-8e6d{background-color:#003532;color:#FFF;font-weight:bold;position:-webkit-sticky;position:sticky;text-align:center;\n  top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-nrix{text-align:center;vertical-align:middle}\n.tg .tg-fg9u{background-color:#036400;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-owtj{background-color:#DAE8FC;text-align:center;vertical-align:top}\n.tg .tg-ok3p{background-color:#ffc702;color:#333333;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-62wo{background-color:#68CBD0;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-c7w8{background-color:#DAE8FC;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-iixg{background-color:#FFFC9E;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-amwm{font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-ziz6{background-color:#C0C0C0;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-o2c7{background-color:#ECF4FF;font-weight:bold;text-align:center;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-8e6d\">Start<\/th>\n    <th class=\"tg-8e6d\">End<\/th>\n    <th class=\"tg-8e6d\">Duration<\/th>\n    <th class=\"tg-8e6d\" colspan=\"6\">9th   Jan 2024<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-nrix\">8:00 AM<\/td>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-fg9u\" colspan=\"6\">Registration<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-owtj\" colspan=\"6\">Plenary Room<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">9:25 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-ok3p\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br><span style=\"font-weight:bold\">Title: Charting the AI-Powered Transformation in the Semiconductor Industry<\/span><br>Sivakumar P R, CEO of Maven Silicon<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:25 AM<\/td>\n    <td class=\"tg-nrix\">9:50 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-62wo\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span> <br> Title: Engineer a Smarter Future &#8211; Faster &#038; Together<br>Ruchir Dixit,   Vice President &amp; Country Manager, Siemens EDA<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:50 AM<\/td>\n    <td class=\"tg-nrix\">10:15 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-e68y\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br> Tittle: Enabling the Next Generation of VLSI Designs with Silicon Lifecycle Management and AI Driven Test <br>Thryambak   Chandilya, Group Director, Hardware Analytics and Test, Synopsys<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:15 AM<\/td>\n    <td class=\"tg-nrix\">10:40 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-62wo\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: Microelectronics Security in the Era of Global Semiconductor Initiatives <br>Prof. Mark M. Tehranipoor, University of Florida, USA<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:40 AM<\/td>\n    <td class=\"tg-nrix\">11:20 AM<\/td>\n    <td class=\"tg-nrix\">00:40<\/td>\n    <td class=\"tg-lk2o\" colspan=\"6\">Tea Break and Inauguration   of Design Contest and Poster Area<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" colspan=\"3\" rowspan=\"3\">   <br>  <br>    <br>  <br>  &nbsp;&nbsp;<br>&nbsp;&nbsp;<br>&nbsp;&nbsp;<\/td>\n    <td class=\"tg-eyg1\">Ballroom1<\/td>\n    <td class=\"tg-c7w8\">Ballroom2<\/td>\n    <td class=\"tg-eyg1\">Ballroom3<\/td>\n    <td class=\"tg-c7w8\">Ballroom4<\/td>\n    <td class=\"tg-eyg1\">Ballroom5<\/td>\n    <td class=\"tg-owtj\">Ballroom6<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-iixg\"><span style=\"font-weight:bold\">Track 13 &#8211; Technical Track<\/span><br> Hardware Security and Emerging Technologies<\/td>\n    <td class=\"tg-iixg\">Track   14 &#8211; Design Contest <br>     Chip Design<\/td>\n    <td class=\"tg-iixg\">Track   15 &#8211; Industry Forum<\/td>\n    <td class=\"tg-iixg\">Track 16   &#8211; Technical Track<br>     Autonomous Systems Design<\/td>\n    <td class=\"tg-iixg\">Track   17 &#8211;  WIE<\/td>\n    <td class=\"tg-iixg\">Track18   &#8211; Poster<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair:<\/span> <br>Prof. Ujjawal Guin, Auburn University<\/td>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair: Prof. Maryam Shojaei Baghini, IIT Bombay<\/span><\/td>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair:<\/span> Sudipto   Das, Quest Global<\/td>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair:<\/span> Prof. Arnab Sarkar, IIT KGP<\/td>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair:<\/span> Prof.   Usha Meheta, Nirma Univ<\/td>\n    <td class=\"tg-p1xr\"><span style=\"font-weight:bold\">Session Chair:<\/span><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:20 AM<\/td>\n    <td class=\"tg-nrix\">11:40 AM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Luminary   Talk (Invited):<\/span> <br>Compiler Assisted Automated Security Countermeasures for   Embedded Crypto-Software<br>     <br>Prof. Chester Rebeiro, IIT Madras<\/td>\n    <td class=\"tg-owtj\">A   Scalable Single-Inductor Multiple-Output DC-DC Converter With Constant   Charge-Transfer and Power-up Sequencing for IoT Applications<br>     <br>     Aditi Chakraborty, Ashish Kumar Jha, Dr. Anupama Deo, Dr. Ashis Maity,   Prof. Amit Patra<br>     (IIT Kharagpur)<\/td>\n    <td class=\"tg-29iq\">Reimagining AI Developement for India<br>Dr. Biswajit Patra, Krutrim<\/td>\n    <td class=\"tg-c7w8\"><span style=\"font-weight:bold\">Luminary Talk   (Invited):<\/span> <br>Challenges in Designing Safe Autonomous Systems <br><br> Prof. Samarjit Chakraborty, UNC Chapel Hill<\/td>\n    <td class=\"tg-k5c1\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Mrs Sunita   Verma, Group Coordinator, R&amp;D MeitY<\/td>\n    <td class=\"tg-jaxz\" rowspan=\"5\"><a href=\"https:\/\/vlsid.org\/poster-presentation\/\" target=\"_blank\" style=\"text-decoration:none;\" rel=\"noopener\">Poster<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:40 AM<\/td>\n    <td class=\"tg-nrix\">12:00 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\" rowspan=\"4\">Harnessing Entropy: RRAM Crossbar-based Unified   PUF and RNG  <br><span style=\"font-weight:bold\">Author:<\/span> Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker,   Simranjeet Singh, Farhad Merchant, Anupam Chattopadhyay, Vikas Rana<br>     <br> Experimental Validation of MemristorAided Logic Using 1T1R TaOx RRAM   Crossbar Array<br><span style=\"font-weight:bold\"> Author:<\/span> Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix C\u00fcppers, Christopher Bengel,  Andr\u00e9 Zambanini, Dennis Nielinger, Sachin   Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana<br>     <br> Designing Hash and Encryption Engines using Quantum Computing <br><span style=\"font-weight:bold\"> Author:<\/span> Suryansh Upadhyay, Rupshali Roy, Swaroop Ghosh <br>     <br>Input Distribution Aware Library of Approximate Adders Based on  Memristor-Aided Logic <br><span style=\"font-weight:bold\"> Author:<\/span> Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler <br>     <br> Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture     <br><span style=\"font-weight:bold\"> Author:<\/span> Noa Aflalo, Eilam Yalon, and Shahar Kvatinsky <\/td>\n    <td class=\"tg-owtj\">A   100 MHz Bandwidth, 73.5dB SNDR, Filtering Continuous-Time Pipelined ADC in   65nm CMOS <br>     <br>     Shanthi Pavan, Nishanth Basavaraj and Saravana Manivannan<br>     (IIT Madras)<\/td>\n    <td class=\"tg-29iq\">Scaling the Generative AI infrastructure with Accelerated Optical and Copper Connectivity<br><br>Lenin Patra, Vice President &amp; CTO &#8211; PHY, Marvell<\/td>\n    <td class=\"tg-owtj\" rowspan=\"4\">Certifiable and Efficient Autonomous Cyber-Physical Systems Design<br><span style=\"font-weight:bold\">Author:<\/span>Shengjie Xu (UNC Chapel Hill, USA), Clara Hobbs (UNC Chapel Hill, USA), Bineet Ghosh (University of Alabama, USA), Parasara Sridhar Duggirala (UNC Chapel Hill, USA), and Samarjit Chakraborty (UNC Chapel Hill, USA) <br>     <br>     <br> Autonomous Automotives on the Edge<br> <span style=\"font-weight:bold\">Author:<\/span> Kaustabha Ray (IBM Research India and ISI), Ansuman Banerjee (ISI) <br>     <br>     <br>Certifying Learning-Enabled Autonomous Cyber Physical Systems<br><span style=\"font-weight:bold\"> Author:<\/span> Suraj Singh, Somnath Hazra, Sumanta Dey and Soumyajit Dey (IIT Kharagpur)<br>     <br>     <br>SMT-based Control Safety Property Checking in Cyber-Physical Systems under   Timing Uncertainties<br><span style=\"font-weight:bold\"> Author: <\/span> Anand Yeolekar (TCS Research Pune and TUM Germany), Ravindra Metta (TCS Research Pune and TUM Germany) and Samarjit Chakraborty (UNC Chapel Hill, USA)<br>     <br><span style=\"font-weight:bold\">Paper Id 220 <\/span><br>Logic locking emulator on FPGA: A conceptual view<br><span style=\"font-weight:bold\">Author:<\/span> Manjith Baby Sarojam Chellam (Assistant Professor); Ramasubramanian   Natarajan (Professor, NIT Tiruchirappalli); Nagi Naganathan (Microsoft,   Raleigh NC, USA)<\/td>\n    <td class=\"tg-k5c1\"><span style=\"font-weight:bold\">Keynote:  <\/span> <br>Dr. Kanchana Bhaaskaran V. S ; Vice &#8211; Chancellor &amp; Pro-Vice Chancellor,   Chennai Campus<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:00 PM<\/td>\n    <td class=\"tg-nrix\">12:20 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-owtj\">ARYABHAT   (Analog Reconfigurable Technology And Bias-scalable Hardware for AI   Tasks)<br>     <br>     Prof. Chetan Singh Thakur, Prof. Shantanu Chakrabartty, Pratik Kumar,   Ankita Nandi, Kurupati Sai Pruthvi Teja<br>     <br>     (IISc Bangalore)<\/td>\n    <td class=\"tg-29iq\" rowspan=\"3\">VLSI: Will it be unprecedented with AI?<br>     <br><span style=\"font-weight:bold\">Moderator<\/span>| Sudipto   Das, Quest Global  <span style=\"font-weight:bold\"> <\/span><br><span style=\"font-weight:bold\">Member<\/span>| Sridhar H Rangarajan, Group Director &#8211; Engineering, Cadence<br>  <span style=\"font-weight:bold\">   Member| <\/span>Bhanu Prakash, Embedded Solutions Manager, Microchip<br>    <span style=\"font-weight:bold\"> Member|<\/span> Biswadeep Chatterjee, Associate Vice President, HCL<br>   <span style=\"font-weight:bold\">  Member|<\/span> Venkatesh Duraisamy, Director, Product Design Engineering, Western   Digital<br>  <span style=\"font-weight:bold\">   Member| <\/span>Avinash Sekhar, Alphawave<br>     <span style=\"font-weight:bold\">Member|<\/span> Praful Pai, Manager &#8211; ECE, Mathworks<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Keynote:<\/span><br> Seema Malhotra, Director, Physical Design Engg, Western Digital<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:20 PM<\/td>\n    <td class=\"tg-nrix\">12:40 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-owtj\">Digitally   Intensive Programmable Sub-sampling Mixer-First Receiver RF front-ends for   IEEE 802.15.4 IoT Applications. <br>     <br>     Raviteja Kammari, Rakesh Varma Rena, Dr. Vijay Shankar Pasupureddi<br>     <br>     (IIT Bhubaneswar)<\/td>\n    <td class=\"tg-29iq\" rowspan=\"2\">Panel Discussion:<br>     Moderator: Prof Ankita Pramanik, IIEST, Shibpur<br>     Member| Anasua Bhowmik, AMD<br>     Member| Viji Ranganna, Google<br>     Member|Seema Jain, Western Digital <br>     Member| Ruchi Jhari, Cadence<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:40 PM<\/td>\n    <td class=\"tg-nrix\">1:00 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-owtj\">Signal-Strength   Detector Based on CMOS-Inverter Supply Current<br>     <br>     Pranav Kumar, Nagendra Krishnapura<br>     <br>     IIT Madras<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">1:00 PM<\/td>\n    <td class=\"tg-nrix\">2:00 PM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-lk2o\" colspan=\"6\">Lunch<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:00 PM<\/td>\n    <td class=\"tg-nrix\">2:25 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-ok3p\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br><span style=\"font-weight:bold\">Title: AI: Creating Tomorrow&#8217;s World<\/span><br>  Sanjay Churiwala,   Corporate Vice President, AMD<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:25 PM<\/td>\n    <td class=\"tg-nrix\">2:50 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-62wo\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br> Title: A Comprehensive Journey Through Holistic GenAI Innovations<br> Srini Maddali,   Senior Vice President Engineering, Qualcomm<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:50 PM<\/td>\n    <td class=\"tg-nrix\">3:15 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-4ztr\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: Scalable SoC\/SiP &#038; AI Integration in Automotive HPC <br>  Prof. Juergen   Becker, Karlsruhe Institute of Technology, Germany <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:15 PM<\/td>\n    <td class=\"tg-nrix\">3:55 PM<\/td>\n    <td class=\"tg-nrix\">00:40<\/td>\n    <td class=\"tg-amwm\" colspan=\"6\"><span style=\"font-weight:bold\">Academic Panel Discussion: <\/span><br>Next-gen Chip   Designers for the AI-driven Semiconductor Industry<br>     Moderator: Sivakumar P R, CEO of Maven Silicon<br>     Member|  Prof. Partha Pratim Das,   Director, Center for Data Science and Analytics, Ashoka University<br>     Member | Prof. Kaushik Roy, Purdue University\t <br>     Member | Sanjay Churiwala, Corporate Vice President, AMD<br>     Member | Prof. V.Ramgopal Rao, Vice-Chancellor, BITS<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:55 PM<\/td>\n    <td class=\"tg-nrix\">4:25 PM<\/td>\n    <td class=\"tg-nrix\">00:30<\/td>\n    <td class=\"tg-lk2o\" colspan=\"6\">Tea Break<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-owtj\" colspan=\"6\">Plenary Room<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-iixg\">Track19  &#8211; Technical Track<br>     AI\/ML in VLSI<\/td>\n    <td class=\"tg-iixg\">Track20- Design Contest <br>    Embedded Systems<\/td>\n    <td class=\"tg-iixg\">Track21   &#8211; Startup Forum Keynote<\/td>\n    <td class=\"tg-iixg\">Track22   &#8211; Student Research Forum\/<br>     PhD Forum<\/td>\n    <td class=\"tg-iixg\">Track23   &#8211; Academic Sponsorship Talk<\/td>\n    <td class=\"tg-iixg\">Track24   &#8211; Poster<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"6%\"> <\/td>\n    <td class=\"tg-p1xr\" width=\"14%\"><span style=\"font-weight:bold\">Session Chair:<\/span> <br>Prof.   Soumyajit Dey, IIT KGP<\/td>\n    <td class=\"tg-kffi\" width=\"14%\"> <span style=\"font-weight:bold\">Session Chair: <br>Arpan Pal, TCS, Kolkata <\/span><\/td>\n    <td class=\"tg-p1xr\" width=\"14%\"> <span style=\"font-weight:bold\">Session Chair: Prof. Gaurab banerjee, IISc Bangalore<\/span><\/td>\n    <td class=\"tg-p1xr\" width=\"14%\"><span style=\"font-weight:bold\">Session Chair: Prof. Manodipan Sahoo, IIT Dhanbad <br>&#038;<br> Prof. Debprasad Das, Central University, Assam <\/span><\/td>\n    <td class=\"tg-p1xr\" width=\"14%\"><span style=\"font-weight:bold\">Session Chair:<\/span><\/td>\n    <td class=\"tg-p1xr\" width=\"14%\"><span style=\"font-weight:bold\">Session Chair:<\/span><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:25 PM<\/td>\n    <td class=\"tg-nrix\">4:45 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-eyg1\"><span style=\"font-weight:bold\">Luminary Talk   (Invited):<\/span><br> <span style=\"font-weight:bold\">Title: <\/span>Bridging Worlds: VLSI &#038; Quantum Electronics<\/br> Dr. S D Sudarsan, Executive Director, CDAC<\/td>\n    <td class=\"tg-owtj\" rowspan=\"4\">AI-Enabled Detection of Autism Spectrum Disorder   (ASD) and Therapy Using Emotional State Recognition<br><span style=\"font-weight:bold\">Author: <\/span>Asmita Zjigyasu, Shivangi, Nancy Gupta, Yash Dharmesh Mogal, Dr. Nanditha   Rao,   IIIT Bangalore<br>     <br>     <br> Gait Phase Identification using Wearable Sensors for Physiotherapy   Assistance<br> <span style=\"font-weight:bold\">Author:<\/span> Rufyid-u-Nissa, Khalid Shaikh, Mohin Shaikh, Arhum Alam, IIT Bombay , AMU<br>     <br>     <br>  ML model to predict the angle of the lower limb and abnormal motion during   sit-to-stand motion<br>  <span style=\"font-weight:bold\">Author:<\/span> Nitheezkant R, Aamod B K , Anshul M , Anmol Shetty, Dr. Madhav Rao, IIIT Bangalore<br>     <br>     <br> Audio Keyword Detection for hands-free control in Automobiles<br> <span style=\"font-weight:bold\">Author:<\/span> Ashwin Rajesh, Venkata Likhith L , IISc Bangalore , IIIT Kancheepuram<br>     <br>     <br> AUTOMATIC MODULATION CLASSIFICATION (AMC) USING MR-CNN ON THE STM32L4   series B-L475E-IOT01A Discovery kit<br> <span style=\"font-weight:bold\">Author: <\/span>Disha Lad, Harshal Patel, Dev Desai, Riya Gupta,      SVNIT, Surat<\/td>\n    <td class=\"tg-29iq\">Translational   Research: The Lab to Fab Journey, <br> <br>Dr. Gaurab Banerjee, IISc<\/td>\n    <td class=\"tg-jaxz\" rowspan=\"4\"><a href=\"https:\/\/vlsid.org\/srf-phd-poster\/\" target=\"_blank\" rel=\"noopener\">SRF &amp; PhD Presentation<\/a><\/td>\n    <td class=\"tg-29iq\">Academic Sponsor-VIT<\/td>\n    <td class=\"tg-jaxz\" rowspan=\"4\"><a href=\"https:\/\/vlsid.org\/poster-presentation\/\" target=\"_blank\" style=\"text-decoration:none;\" rel=\"noopener\">Poster<\/a><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:45 PM<\/td>\n    <td class=\"tg-nrix\">5:05 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\" rowspan=\"3\"><span style=\"font-weight:bold\">Paper Id 366 <\/span><br>FLIP: An Artificial Neural Network-based   Post-routing Incremental Placer <br><span style=\"font-weight:bold\">Author:<\/span> Pranav Jain (Indraprastha Institute of Information Technology Delhi   (IIITD)); Gagandeep (Indraprastha Institute of Information Technology Delhi   (IIITD)); Sneh Saurabh (Indraprastha Institute of Information   Technology)<br>     <br><span style=\"font-weight:bold\">Paper Id 393 <\/span> <br> Machine Learning based Waveform Predictions using Discrete Wavelet   Transform for Automated Verification of Analog and Mixed Signal Integrated   Circuits<br><span style=\"font-weight:bold\">Author:<\/span> Dhurga Devi J (College of Engineering Guindy, Anna University);   Selvi Ravindran (Anna University); Bama Srinivasan (Anna University);   Lakshmanan Balasubramanian (Texas Instruments (India) Pvt. Ltd.); Ranjani   Parthasarathi (CEG Campus, Anna University); Ramakrishna P V (CEG Campus,   Anna University)<br>     <br><span style=\"font-weight:bold\">Paper Id 412 <\/span> <br> Reinforcement Learning based Droplet Routing Technique in Hexagonal Digital   Microfluidic Biochips using Dueling Network<br> <span style=\"font-weight:bold\">Author:<\/span> Amartya Dutta (B. P. Poddar Institute of Management and Technology,   Kolkata); Riya Majumder (Netaji Subhash Engineering College); Rajat Kumar Pal   (University of Calcutta)<br>     <br><span style=\"font-weight:bold\">Paper Id 205 <\/span><br>SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking<br><span style=\"font-weight:bold\">Author:<\/span> Jugal Gandhi (AcSIR at CSIR-CEERI); Rishi Agarwal (BITS Pilani);   Anish Mall (BITS Pilani); Diksha Shekhawat (AcSIR at CSIR-CEERI); M. Santosh   (CSIR-CEERI); Jai Gopal Pandey (CSIR-CEERI)<\/td>\n    <td class=\"tg-29iq\">The   role of Chip Incubator in Indian Ecosystem<br>  <br>Dr. Siva Vanjari, FabCI\/IITH<\/td>\n    <td class=\"tg-29iq\">Academic Sponsor- Vignan<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:05 PM<\/td>\n    <td class=\"tg-nrix\">5:25 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\">Current   Government Initiatives <br><br>Shri Nishit Gupta, Meity, GOI<\/td>\n    <td class=\"tg-29iq\">Academic Sponsor-UEM<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:25 PM<\/td>\n    <td class=\"tg-nrix\">5:45 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\">Fundrising   for the Startup Journey<br> <br>Mr. Avelo Roy, Kolkata Ventures<\/td>\n    <td class=\"tg-29iq\">Academic Sponsor &#8211; Supreme Knowledge Foundation <br> <br> <br>  <b> <hr style=\"height:1px;color:black; background-color:#000; width:110%; margin-left:0px; float:left;\"> <\/b>  <br> <br> Academic Sponsor &#8211; Netaji Subhas Engineering College<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-ziz6\" colspan=\"6\">Networking Break<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">6:15 PM<\/td>\n    <td class=\"tg-nrix\">6:40 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-ql2y\" colspan=\"6\"><span style=\"font-weight:bold\">Banquet Talk:<\/span><br>Title: Analog Spiking Processors for   Intelligent Sensing<br>Dr. Aditya Dalakoti, Principal   Engineering Manager, Innatera Nanosystems <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">6:40 PM<\/td>\n    <td class=\"tg-nrix\">7:10 PM<\/td>\n    <td class=\"tg-nrix\">00:30<\/td>\n    <td class=\"tg-k4xr\" colspan=\"6\">Award Ceremony<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">7:10 PM<\/td>\n    <td class=\"tg-nrix\">7:35 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-ql2y\" colspan=\"6\"><span style=\"font-weight:bold\">Banquet Talk:<\/span> <br>Title: Open Platform for the Embodied   AI Era  <br>Prof. Luca Benini,  ETH Z\u00fcrich,   Switzerland<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">7:35 PM<\/td>\n    <td class=\"tg-nrix\">7:45 PM<\/td>\n    <td class=\"tg-nrix\">00:10<\/td>\n    <td class=\"tg-fg9u\" colspan=\"6\">Address by General Chair VLSID 2025<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">7:45 PM<\/td>\n    <td class=\"tg-nrix\">8:45 PM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-o2c7\" colspan=\"6\">Cultural Program<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">8:30 PM<\/td>\n    <td class=\"tg-nrix\">10:00 PM<\/td>\n    <td class=\"tg-nrix\">01:30<\/td>\n    <td class=\"tg-gxkf\" colspan=\"6\">Banquet Dinner<\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-getwid-tabs__nav-link\"><h6 class=\"wp-block-getwid-tabs__title-wrapper\"><a href=\"#\"><span class=\"wp-block-getwid-tabs__title\">10th Jan<\/span><\/a><\/h6><\/div><div class=\"wp-block-getwid-tabs__tab-content-wrapper\"><div class=\"wp-block-getwid-tabs__tab-content\">\n<style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-spacing:0;margin:0px auto;}\n.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;\n  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-p1xr{background-color:#34696D;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-29iq{background-color:#FFFFC7;text-align:center;vertical-align:top}\n.tg .tg-eyg1{background-color:#FFFFC7;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-8e6d{background-color:#003532;color:#FFF;font-weight:bold;position:-webkit-sticky;position:sticky;text-align:center;\n  top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-nrix{text-align:center;vertical-align:middle}\n.tg .tg-xjuq{background-color:#009901;color:#FFF;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-owtj{background-color:#DAE8FC;text-align:center;vertical-align:top}\n.tg .tg-amwm{font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-ksec{background-color:#FFFFC7;color:#013300;font-weight:bold;text-align:center;vertical-align:top}\n.tg .tg-zjgg{background-color:#999903;color:#FFF;font-weight:bold;text-align:center;vertical-align:middle}\n.tg .tg-xmkd{background-color:#EFEFEF;text-align:center;vertical-align:top}\n.tg .tg-c7w8{background-color:#DAE8FC;font-weight:bold;text-align:center;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;margin: auto 0px;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-8e6d\">Start<\/th>\n    <th class=\"tg-8e6d\">End<\/th>\n    <th class=\"tg-8e6d\">Duration<\/th>\n    <th class=\"tg-8e6d\" colspan=\"6\">10th   Jan 2024<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-nrix\">8:00 AM<\/td>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-xjuq\" colspan=\"6\">Registration<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-owtj\" colspan=\"6\">Plenary Room<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:00 AM<\/td>\n    <td class=\"tg-nrix\">9:25 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-eyg1\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span> <br>Title: Polynomial Formal Verification for Ensuing Processor Correctness<br>Prof. Rolf   Drechsler, University of Bremen, Germany<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">9:25 AM<\/td>\n    <td class=\"tg-nrix\">10:10 AM<\/td>\n    <td class=\"tg-nrix\">00:45<\/td>\n    <td class=\"tg-amwm\" colspan=\"6\">Panel Discussion: <br>Government Initiatives and Efforts for Semiconductors &amp; VLSI Design<br><br>Moderator| Chitra Hariharan, Secretary, VLSI Society of India<br>Member | Rajeev Kumar, Principal Secretary, Dept of IT and Electronics, Govt of WB<br>Member |  Debashis Dutta, Executive Vice President and Chief Scientist at Reliance Jio Infocom Limited, Former Group Coordinator R&amp;D, MeitY<br>Member | Aditya Kumar Sinha, Director at C-DAC Patna &amp; C-DAC Kolkata<br><br><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:10 AM<\/td>\n    <td class=\"tg-nrix\">10:35 AM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-ksec\" colspan=\"6\"><span style=\"font-weight:bold;color:#000\">Fireside Chat:<\/span><br><span style=\"font-weight:bold;color:#000\"> Future of Research and Technology Development for Semiconductor Technology &amp; Chip Design<\/span><br><span style=\"font-weight:bold;color:#000\">Moderator| Dr. Satya Gupta, President, VLSI Society of India<\/span><br><span style=\"color:#000\">Member| Prof. Subhasish Mitra, Stanford University, USA<\/span><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:35 AM<\/td>\n    <td class=\"tg-nrix\">10:50 AM<\/td>\n    <td class=\"tg-nrix\">00:15<\/td>\n    <td class=\"tg-amwm\" colspan=\"6\"><span style=\"font-weight:bold\">Talk: WEBEL@50 &#8211; a new beginning<\/span><br>Sanjay Kumar Das, MD, WEBEL<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">10:50 AM<\/td>\n    <td class=\"tg-nrix\">11:20 AM<\/td>\n    <td class=\"tg-nrix\">00:30<\/td>\n    <td class=\"tg-zjgg\" colspan=\"6\">Tea Break<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" colspan=\"3\" rowspan=\"3\">   <br>  <br>    <br>  <br>  &nbsp;&nbsp;<br>&nbsp;&nbsp;<br>&nbsp;&nbsp;<\/td>\n    <td class=\"tg-29iq\">Ballroom1<\/td>\n    <td class=\"tg-owtj\">Ballroom2<\/td>\n    <td class=\"tg-29iq\">Ballroom3<\/td>\n    <td class=\"tg-owtj\">Ballroom4<\/td>\n    <td class=\"tg-29iq\">Ballroom5<\/td>\n    <td class=\"tg-owtj\">Ballroom6<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-xmkd\">Track25 &#8211; Technical Track<br>     AI\/ ML<\/td>\n    <td class=\"tg-xmkd\">Track26   &#8211; Technical Track<br>     AMS<\/td>\n    <td class=\"tg-xmkd\">Track27 &#8211; Startup   Forum<\/td>\n    <td class=\"tg-xmkd\">Track28   &#8211; Technical Track<br>     Hardware Security<\/td>\n    <td class=\"tg-xmkd\">Track29   &#8211; Technical Track<br>     Advanced Process\/Material, Device Design and Modelling<\/td>\n    <td class=\"tg-xmkd\">Track30   &#8211; Low-power <br>     Digital Systems<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-p1xr\">Session Chair: Prof. Shanti Prasad Maity, IIEST<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Soumya Pandit, CU<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Atul Prakash Agarwal, Apt Software Avenues Pvt. Ltd.<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Subhajit Das, SR Univ<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Sanatan Chattopadhyay, CU<\/td>\n    <td class=\"tg-p1xr\">Session Chair: Prof.   Indrajit Chakraborty, IIT KGP<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:20 AM<\/td>\n    <td class=\"tg-nrix\">11:40 AM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\">Luminary   Talk (Invited): <br> Challenges of Computing System Design in the Generative AI Era <br> <br> Krishnan Kailas, IBM Thomas J. Watson Research Center<\/td>\n    <td class=\"tg-owtj\">Luminary   Talk (Invited): <br>Transmission-Line-Based Phase Shifters for Millimeter Wave Systems <br> <br> Prof. Sankaran Aniruddhan, IIT Madras<\/td>\n    <td class=\"tg-29iq\">Title: Startup Intellectual Property (IPR) Awareness <br>Souvik Basu, Director (Program Management), Qualcomm<\/td>\n    <td class=\"tg-owtj\">Luminary   Talk (Invited): <br>Is your Compiler Secure? <br><br>Prof. Chandan Karfa, IITG<\/td>\n    <td class=\"tg-29iq\">Luminary Talk (Invited): <br>High-Frequency Characterization and Modeling of Low and High Voltage FinFETs for RF SoCs <br> <br> Prof. Yogesh S. Chauhan, IIT Kanpur<\/td>\n    <td class=\"tg-owtj\">Luminary Talk   (Invited): <br>An overview of High Bandwidth Memory (HBM) &#8211; the cortex of today&#8217;s Generative AI hardware <br> <br> Venkatraghavan Bringivijayraghavan, Senior Director, Micron<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">11:40 AM<\/td>\n    <td class=\"tg-nrix\">12:00 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID: 22<\/span> <br>Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of   Deep Learning<br><br><span style=\"font-weight:bold\">Authors:<\/span><br>Davide   Giacomini (University of Illinois Chicago); Maeesha BinteHashem   (UniversityofIllinoisChicago); Jeremiah Suarez (Illinois Mathematics and   Science Academy); SWARUP BHUNIA (University of Florida); Amit Ranjan Trivedi   (University of Illinois Chicago)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 270   <\/span>  <br>A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi   using a 130 nm SOI CMOS Technology<br>     <br><span style=\"font-weight:bold\">Author: <\/span><br>Indrajit Das   (Globalfoundries); Hari Kishore Kakara (Principal Engineer, GlobalFoundries);   Vasudeva Reddy (Member of Technical Staff, GlobalFoundries); Venkata Vanukuru   (GLOBALFOUNDRIES)<\/td>\n    <td class=\"tg-29iq\">Vishal Sharma, PE, iDEX DIO<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  87  <\/span>   <br>Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment   on FPGAs<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Debayan Das   (Indian Institute of Science); Majid Sabbagh (Northeastern University); Rana   Elnaggar (Intel Corporation); Guang Chen (Intel Corporation); Sayak Ray   (Intel Corporation); Jason M. Fung (Intel Corporation)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  44 <\/span>    <br>Experimental Demonstration of CeO\u2082-Based Tunable Gated Memristor for RRAM   Applications<br>     <br><span style=\"font-weight:bold\">Author: <\/span><br>Surya Shankar   Dan (Professor, BITS Pilani)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  150  <\/span>   <br>Design of VFC with Programmable Frequency Ramp to control on-chip switching   current profile<br><br><span style=\"font-weight:bold\">Authors: <\/span><br>Pritam   Bhattacharjee (Vellore Institute of Technology, Chennai Campus); ALAK   MAJUMDER (NIT Arunachal Pradesh)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:00 PM<\/td>\n    <td class=\"tg-nrix\">12:20 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  45<\/span>  <br>Hardware-based Detection of Malicious Firmware Modification in   Microgrids<br><br><span style=\"font-weight:bold\">Authors: <\/span><br>Amisha   Srivastava (University of Texas at Dallas); Sneha Thakur (IEEE Member);   Abraham Peedikayil Kuruvila (Samsung Electronics America); Poras T. Balsara   (The University of Texas at Dallas); Kanad Basu (The University of Texas at   Dallas)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  284<\/span>     <br>A 1.6 &#8211; 2.5 GHz Receiver for Software Defined Radio with High Linearity   Mode<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> Gopikrishna   Vijayakumar (Indian Institute of Technology Hyderabad); Abhishek Kumar   (Indian Institute of Technology Hyderabad)<\/td>\n    <td class=\"tg-29iq\">Titile:  World&#8217;s first &#8211; Fully Hardware based encryption Device (ABHED1) <br> Sumit Kathavekar, Manager (Design Team), Chipspirit Technologies<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  163 <\/span>    <br>Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and   Containment<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Akash   Panzade (Indian Institute of Technology Kanpur); Deepak Kumar (Indian   Institute of Technology Kanpur); Mahendra Rathor (IIT-BHU Varanasi); Urbi   Chatterjee (Indian Institute of Technology Kanpur)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  63 <\/span>    <br>Artificial neural network-based solution for PSP MOSFET model card   extraction<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Alba Ordonez   (STMicroelectronics); fabien gilibert (ST Microelectronics); Francois Paolini   (ST Microelectronics); Pascal Urard (ST Microelectronics); Roberto Guizzeti   (ST Microelectronics); Lioua Labrak (INL Lyon); John Samuel (INL Lyon)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  174 <\/span>  &nbsp;&nbsp;<br>OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array   Design for an Image Processing Application<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Dantu   Nandini Devi (International Institute of Information Technology Bangalore);   Gandi Ajay Kumar (International Institute of Information Technology   Bangalore); Bindu G Gowda (International Institute of Information Technology   Bangalore); Madhav Rao (International Institute of Information   Technology-Bangalore)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:20 PM<\/td>\n    <td class=\"tg-nrix\">12:40 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID: 91<\/span> <br>Multiplierless In-filter Computing for tiny ML Platforms<br><br><span style=\"font-weight:bold\">Authors:<\/span> <br>Abhishek   Nair (IISc); Pallab Kumar Nath (Pandit Deendayal Energy University); Shantanu   Chakrabartty (Washington University in St. Louis); Chetan Thakur (Indian   Institute of Science, Bangalore)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 395<\/span>   &nbsp;&nbsp;<br>A Low Power and Low Noise, Self-Body Biased Low Noise Amplifier.<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Jyoti Priya   (IITR); Darshak Bhatt (Indian Institute of Technology Roorkee)<\/td>\n    <td class=\"tg-29iq\" > Sukanta Mitra, President, ANTS Global Systems<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  196<\/span>   &nbsp;&nbsp;<br>Enhancing Hardware Trojan Security through Reference-Free Clustering using   Representatives<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ashutosh   Ghimire (Wright State University); Fathi Amsaad (Wright State University);   Mohammed Alkurdi (Wright State University)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  182 <\/span>    <br>Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and   Optimization of Back Gate Parameters<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Monika   Kumari (IIT(ISM), Dhanbad); Manodipan Sahoo (IIT(ISM),Dhanbad)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  224  <\/span>   <br>A 0.8 V, 2.47 \u00b5W, SEU Tolerant Tri-State Inverter based SRAM Cell for SoC   Applications     <br><br><span style=\"font-weight:bold\">Author:<\/span> <br>Srujana   Pillay (National Institute of Technology, Goa)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">12:40 PM<\/td>\n    <td class=\"tg-nrix\">1:00 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID: 142<\/span> <br>Low-Complexity Classification Technique and Hardware-Efficient   Classify-Unit Architecture for CNN Accelerator<br> <br><span style=\"font-weight:bold\">Authors: <\/span><br>Md Najrul   Islam (Indian Institute of Technology Mandi); Rahul Shrestha (Indian   Institute of Technology Mandi); Shubhajit Roy Chowdhury (IIT Mandi)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 396 <\/span>    <br>Closed Form Expression of Input Matching of a Wideband Single-Ended to   Differential LNA<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Sanchari Das   (Department of Electrical Engineering, University at Buffalo); Bibhu Datta   Sahoo (Department of Electrical Engineering, University at Buffalo)<\/td>\n    <td class=\"tg-29iq\" ><\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 201 <\/span>     <br>Stealthy SWAPs: Adversarial SWAP Injection in Multi-Tenant Quantum   Computing.<br>    <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Suryansh   Upadhyay (Penn State University); Swaroop Ghosh (Pennsylvania State   University)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  341   <\/span>  <br>Understanding 2-Propanol Sensing Mechanism of Pd Modified Graphene Based   Gas Sensor Devices using DFT Study<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Indranil   Maity (Assistant Professor, Department of ECE, Institute of Engineering and   Management (IEM), Kolkata); Shivam Das (Institute of Engineering and   Management (IEM-K), Kolkata); Rishav Dutta (Institute of Engineering and   Management (IEM-K), Kolkata); Indrajit Maity (Institute of Radio Physics and   Electronics (IRPE)  University of   Calcutta (CU)); Malay Ganguly (Institute of Engineering and Management   (IEM-K), Kolkata)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  234 <\/span>    <br>Design and Analysis of an Area and Power Efficient Programmable Delay   Cell<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Kuntal   Chakraborty (NIT Arunachal Pradesh); Jai Gopal Pandey (CEERI Pilani); Abir J   Mondal (NIT Arunachal Pradesh)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">1:00 PM<\/td>\n    <td class=\"tg-nrix\">2:00 PM<\/td>\n    <td class=\"tg-nrix\">01:00<\/td>\n    <td class=\"tg-zjgg\" colspan=\"6\">Lunch<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:00 PM<\/td>\n    <td class=\"tg-nrix\">2:45 PM<\/td>\n    <td class=\"tg-nrix\">00:45<\/td>\n    <td class=\"tg-c7w8\" colspan=\"6\"><span style=\"font-weight:bold\">Panel   Discussion:<\/span><br>Advancing to the Next Frontier in AI\/ML Driven EDA <br>     <span style=\"font-weight:bold\">Moderator:<\/span> Sumit Goswami, Sr. Director of Engineering, Qualcomm<br>     <span style=\"font-weight:bold\">Member | <\/span>Sudeep Mondal, Director R&amp;D, Synopsys<br>   <span style=\"font-weight:bold\">  Member | <\/span>Dhiraj Goswami, Corporate Vice President R&amp;D, Cadence<br>     <span style=\"font-weight:bold\">Member | <\/span>Ruchir Dixit, Country Manager, Siemens EDA<br>     <span style=\"font-weight:bold\">Member |<\/span> Himanshu Rawal, Sales Manager Semicon India business, Ansys<br>    <span style=\"font-weight:bold\"> Member |<\/span> Dipanjan Gope, CEO, Simyog Technology\t                   <\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">2:45 PM<\/td>\n    <td class=\"tg-nrix\">3:10 PM<\/td>\n    <td class=\"tg-nrix\">00:25<\/td>\n    <td class=\"tg-eyg1\" colspan=\"6\"><span style=\"font-weight:bold\">Keynote:<\/span><br>Title: AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency <br> Prof. Yiran   Chen, Duke University, USA<br><\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:10 PM<\/td>\n    <td class=\"tg-nrix\">3:55 PM<\/td>\n    <td class=\"tg-nrix\">00:45<\/td>\n    <td class=\"tg-amwm\" colspan=\"6\"><span style=\"font-weight:bold\">Panel   Discussion: <\/span><br>ESDM Opportunities in India <br>    <span style=\"font-weight:bold\"> Moderator:<\/span> Mr. Srinivasa Kakumanu, MosChip<br>     <span style=\"font-weight:bold\">Member|<\/span> Raghu Panicker, CEO, Kaynes Technologies  <br> <span style=\"font-weight:bold\">Member|<\/span> Prosit Mukherjee, Sr. Director Engg &#038; Head, Noida Design Center<br>   <span style=\"font-weight:bold\"> Member| <\/span>Taher Madraswala, Strategic Client Partner-Semiconductor, Quest   Global<br>     <span style=\"font-weight:bold\">Member| <\/span>Prof. Debesh Das, Jadavpur University<br>     <span style=\"font-weight:bold\">Member|<\/span> Nishit Gupta, Scientist E, MeitY and Director (Technology), India   Semiconductor Mission<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">3:55 PM<\/td>\n    <td class=\"tg-nrix\">4:25 PM<\/td>\n    <td class=\"tg-nrix\">00:30<\/td>\n    <td class=\"tg-zjgg\" colspan=\"6\">Tea Break<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-nrix\"> <\/td>\n    <td class=\"tg-xmkd\">Track31   &#8211; Technical Track<br>     AI\/ ML<\/td>\n    <td class=\"tg-xmkd\">Track32   &#8211; Technical Track<br>     AMS<\/td>\n    <td class=\"tg-xmkd\">Track33 &#8211;  <\/td>\n    <td class=\"tg-xmkd\">Track34-Technical   Track<br>     Hardware Security<\/td>\n    <td class=\"tg-xmkd\">Track35   &#8211; Technical Track<br>     Advanced Process\/Material, Device Design and Modelling<\/td>\n    <td class=\"tg-xmkd\">Track36   &#8211; Low-power <br>     Digital Systems<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"5%\"> <\/td>\n    <td class=\"tg-nrix\" width=\"6%\"> <\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Jimson Mathew, IIT Patna<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Bibhoo Dutta Sahoo, Univ Buffalo<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair:<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Rajat Subhra Chakraborty, IIT KGP<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Anirban Bhattacharyya, CU<\/td>\n    <td class=\"tg-p1xr\" width=\"14%\">Session Chair: Prof.   Urbi Chatterjee, IIT Kanpur<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:25 PM<\/td>\n    <td class=\"tg-nrix\">4:45 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  214 <\/span>    <br>Bit-Beading: Stringing bit-level MAC results for Accelerating Neural   Networks<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Zeeshan   Anwar (Indian Institute of Technology Guwahati); Imlijungla Longchar (Indian   Institute of Technology Guwahati); Hemangee Kapoor (Indian Institute of   Technology Guwahati)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  389  <\/span>   <br>Generation of Asymmetric Triangular Pulse by A Dispersion and Non-linearity   Engineered Silicon Core Optical Fiber<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Atrayee   Mishra (Research scholar); Binoy Ghosh (Indian Institute of Engineering   Science and Technology, Shibpur); Dipankar Ghosh (Assistant Professor,   Department of Basic Science ,MCKV Institute of Engineering, Liluah, Howrah);   Mousumi Basu (Professor, IIEST)<br>     <\/td>\n    <td class=\"tg-eyg1\" rowspan=\"4\"> <br><br><br><br><br><br><br><br><br><\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  272<\/span>   &nbsp;&nbsp;<br>SRIL: Securing Registers from Information Leakage at Register Transfer   Level<br> <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Priyanka   Panigrahi (Indian Institute of Technology Guwahati, India); Vignesh   Ravichandra Rao (Indian Institute of Technology Guwahati, India); Thockchom   Birjit Singha (Indian Institute of Technology Guwahati, India); Chandan Karfa   (Indian Institute of Technology Guwahati)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\"> Paper ID:  374 <\/span>    <br>Design of MoS2 based Inverter Circuits considering Interface Trap   effect<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Sarath S   (National Institute of Technology Calicut); Darshni Manekar (National   Institute of Technology Calicut); Rajendra Prasad Shukla (University of   Twente); Chandan Yadav (National Institute of Technology Calicut)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  246 <\/span>   <br>EBACA: Efficient Bfloat16-based Activation Function Implementation Using   Enhanced CORDIC Architecture<br> <br><span style=\"font-weight:bold\">Authors: <\/span> <br>Vinay   Rayapati (international institute of information technology, bangalore);   Sanampudi Gopala Krishna Reddy (international institute of information   technology, bangalore); Ajay Kumar Gandi (international institute of   information technology, bangalore); Gogireddy Ravi Kiran Reddy (international   institute of information technology, bangalore); Madhav Rao (International   Institute of Information Technology-Bangalore)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">4:45 PM<\/td>\n    <td class=\"tg-nrix\">5:05 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  379 <\/span>    <br>Low Complexity High Speed Deep Neural Network Augmented Wireless Channel   Estimation<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Syed Asrar   ul haq (Indraprastha Institute of Information Technology Delhi); Varun Singh   (Indraprastha Institute of Information Technology Delhi); Bhanu Teja Tanaji   (Indraprastha Institute of Information Technology Delhi); Sumit Darak   (IIIT-Delhi)<br>     <\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 141 <\/span>  <br>An On-chip Thermoelectric Cooler Controller With Improved Driving Current   of 2 A at 0.5 \u2126 Load<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Sowmyashree   Srinivas (IIT Mandi); Hitesh Shrimali (Indian Institute of Technology Mandi)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  311   <\/span>     <br>ROBUST: RTL Obfuscation Using Bi-functional Polymorphic Operators<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Haimanti   Chakraborty (University of Cincinnati); Ranga Vemuri (University of   Cincinnati)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  409 <\/span>    <br>Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs:   A Machine Learning Perspective<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Vivek Kumar   (NIT Uttarakhand &amp; IIT Roorkee); Nischal Anand (NIT Uttarakhand); Rohit   Rai (NIT Uttarakhand); Sneha Chauhan (NIT Uttarakhand); Jyoti Patel (Indian   Institute of technology Roorkee)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  289  <\/span>   <br>FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with   Scan Insertion for Carry Chain Based Multi-level Logic Implementation<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ayan   Palchaudhuri (Indian Institute of Technology Bhubaneswar); Anindya Sundar   Dhar (Indian Institute of Technology Kharagpur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:05 PM<\/td>\n    <td class=\"tg-nrix\">5:25 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID: 424  <\/span>   <br>FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory   Computing<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Yathin   Attuluri (International Institute of Information Technology Bangalore);   Ruchit Chudasama (IIT Gandhinagar); Kailash Prasad (Indian Institute of   Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology   Gandhinagar)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 325  <\/span>   <br>Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic   Body Biasing Scheme<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Rohan Sinha   (Texas Instruments India Pvt. Ltd.); Devraj M. Rajagopal (Texas Instruments   India Pvt. Ltd); Aditya Madhavan (Texas Instruments India Pvt. Ltd)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  364  <\/span>   <br>Security Implications of Approximation: A Study of Trojan Attacks on   Approximate Adders and Multipliers<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Vishesh   Mishra (Indian Institute of Technology Kanpur); Sparsh Mittal (IIT Roorkee);   Nirbhay Mishra (Chandigarh University); Rekha Singhal (TCS Research)<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  50 <\/span>    <br>Experimental Demonstration of SnO\u2082 Nanofiber-Based Memristors and Their   Data-Driven Modeling for Electronic Circuit Applications<br>     <br><span style=\"font-weight:bold\">Author:<\/span> <br>Surya Shankar   Dan (Professor, BITS Pilani)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  410<\/span> <br>A High Performance and Low Power Subthreshold Voltage Level Shifter   Design<br><br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ananya   Kapoor (Delhi Technological University); Ayush Thapar (Delhi Technological   University); Chaitanya Shanker Jha (Delhi Technological University); Dr.   Inder Kumar Choudhary (Delhi Technological University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:25 PM<\/td>\n    <td class=\"tg-nrix\">5:45 PM<\/td>\n    <td class=\"tg-nrix\">00:20<\/td>\n    <td class=\"tg-29iq\"><span style=\"font-weight:bold\">Paper ID:  429  <\/span>   <br>COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN   Hardware Accelerators<br>     <br><span style=\"font-weight:bold\">Authors: <\/span><br>Vrajesh   Patel (Indian Institute of Technology Gandhinagar); Neel Shah (Indian   Institute of Technology Gandhinagar); Aravind Krishna (Indian Institute of   Technology Gandhinagar); Tom Glint (Indian Institute of Technology   Gandhinagar); Abdul Ronak (Indian Institute of Technology Gandhinagar);   Joycee Mekie (Indian Institute of Technology Gandhinagar)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 64 <\/span>     <br>Wear Leveling-Aware Active Battery Cell Balancing<br>     <br><span style=\"font-weight:bold\">Authors:<\/span><br> Enrico   Fraccaroli (University of North Carolina at Chapel Hill); Seongik Jang   (Hyundai Motor Company); Logan Stach (UNC Chapel Hill); Hoeseok Yang (Santa   Clara University); Sangyoung Park (Technical University of Berlin); Samarjit   Chakraborty (UNC Chapel Hill)<\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID: 433 <\/span>    <br>Quantifying the Efficacy of Logic Locking Methods<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Deepali Garg   (Carnegie Mellon University); Joseph Sweeney (Amazon); Larry Pileggi   (Carnegie Mellon University)<\/td>\n    <td class=\"tg-eyg1\"><\/td>\n    <td class=\"tg-owtj\"><span style=\"font-weight:bold\">Paper ID:  157 <\/span>    <br>Power Integrity Analysis for Interoperability of BoW Chiplet   Interfaces<br>     <br><span style=\"font-weight:bold\">Authors:<\/span> <br>Ishan Mishra   (Indian Institute of Technology Bombay); Jayaprakash Balachandran (d-Matrix);   Wen-Sin Liew (d-Matrix Inc.); Elad Alon (Blue Cheetah Analog Design Inc.);   Srinivas Venkataraman (Meta Platforms Inc.); Shalabh Gupta (IIT Bombay)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-nrix\">5:45 PM<\/td>\n    <td class=\"tg-nrix\">6:30 PM<\/td>\n    <td class=\"tg-nrix\">00:45<\/td>\n    <td class=\"tg-amwm\" colspan=\"6\">Wrap Up Session<\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n<\/div><\/div>\n<\/div>\n<\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"blocksy_meta":{"styles_descriptor":{"styles":{"desktop":"","tablet":"","mobile":""},"google_fonts":[],"version":5}},"_links":{"self":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/2762"}],"collection":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/comments?post=2762"}],"version-history":[{"count":577,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/2762\/revisions"}],"predecessor-version":[{"id":4995,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/2762\/revisions\/4995"}],"wp:attachment":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/media?parent=2762"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}