{"id":4108,"date":"2023-12-19T09:53:09","date_gmt":"2023-12-19T09:53:09","guid":{"rendered":"https:\/\/vlsid.org\/?page_id=4108"},"modified":"2023-12-19T09:53:13","modified_gmt":"2023-12-19T09:53:13","slug":"poster-presentation","status":"publish","type":"page","link":"https:\/\/vlsid.org\/poster-presentation\/","title":{"rendered":"Poster Presentation"},"content":{"rendered":"\n<div class=\"wp-block-getwid-section alignfull\"><div class=\"wp-block-getwid-section__wrapper\"><div class=\"wp-block-getwid-section__inner-wrapper\"><div class=\"wp-block-getwid-section__background-holder\"><div class=\"wp-block-getwid-section__background\"><\/div><div class=\"wp-block-getwid-section__foreground\"><\/div><\/div><div class=\"wp-block-getwid-section__content\"><div class=\"wp-block-getwid-section__inner-content\">\n<style type=\"text\/css\">\n.tg  {border-collapse:collapse;border-color:#9ABAD9;border-spacing:0;}\n.tg td{background-color:#EBF5FF;border-color:#9ABAD9;border-style:solid;border-width:1px;color:#444;\n  font-family:Arial, sans-serif;font-size:14px;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg th{background-color:#409cff;border-color:#9ABAD9;border-style:solid;border-width:1px;color:#fff;\n  font-family:Arial, sans-serif;font-size:14px;font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}\n.tg .tg-hmp3{background-color:#D2E4FC;text-align:left;vertical-align:top}\n.tg .tg-baqh{text-align:center;vertical-align:top}\n.tg .tg-rz9m{position:-webkit-sticky;position:sticky;text-align:center;top:-1px;vertical-align:top;will-change:transform}\n.tg .tg-j0tj{background-color:#D2E4FC;text-align:center;vertical-align:top}\n.tg .tg-0lax{text-align:left;vertical-align:top}\n@media screen and (max-width: 767px) {.tg {width: auto !important;}.tg col {width: auto !important;}.tg-wrap {overflow-x: auto;-webkit-overflow-scrolling: touch;}}<\/style>\n<div class=\"tg-wrap\"><table class=\"tg\">\n<thead>\n  <tr>\n    <th class=\"tg-rz9m\">Submission&nbsp;&nbsp;&nbsp;ID<\/th>\n    <th class=\"tg-rz9m\">Title<\/th>\n    <th class=\"tg-rz9m\">Authors with&nbsp;&nbsp;&nbsp;Affiliations<\/th>\n  <\/tr>\n<\/thead>\n<tbody>\n  <tr>\n    <td class=\"tg-j0tj\">5<\/td>\n    <td class=\"tg-hmp3\">Low&nbsp;&nbsp;&nbsp;Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High&nbsp;&nbsp;&nbsp;Speed Application<\/td>\n    <td class=\"tg-hmp3\">Shriharsh&nbsp;&nbsp;&nbsp;Prasad Behera (National Institute of Technology Raipur); Mahesh Vaidya&nbsp;&nbsp;&nbsp;(Indian Institute of Science); Alok Naugarhiya (National Institute of&nbsp;&nbsp;&nbsp;Technology Raipur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">236<\/td>\n    <td class=\"tg-0lax\">K-means&nbsp;&nbsp;&nbsp;Clustering with ANN based Classification to Predict Current-Voltage&nbsp;&nbsp;&nbsp;Characteristics of Advanced FETs<\/td>\n    <td class=\"tg-0lax\">Om&nbsp;&nbsp;&nbsp;Maheshwari (Indian Institute of Technology Gandhinagar); Dev Vyas (Pandit&nbsp;&nbsp;&nbsp;Deendayal Energy University); Nihar Mohapatra (Associate Professor)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">261<\/td>\n    <td class=\"tg-hmp3\">Improving&nbsp;&nbsp;&nbsp;Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis<\/td>\n    <td class=\"tg-hmp3\">SHIVENDRA&nbsp;&nbsp;&nbsp;SINGH (IIIT Delhi); EKTA TIWARI (IIIT Delhi); ABHINAV GUPTA (IIIT Delhi);&nbsp;&nbsp;&nbsp;SNEH SAURABH (IIIT Delhi)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">98<\/td>\n    <td class=\"tg-0lax\">Flux&nbsp;&nbsp;&nbsp;Controlled Grounded Meminductor Emulator Using Single DVCCTA<\/td>\n    <td class=\"tg-0lax\">Nidhee&nbsp;&nbsp;&nbsp;Bhuwal (Dr Shyama Prasad Mukherjee International Institute of Information&nbsp;&nbsp;&nbsp;Technology, Naya Raipur); Manoj Kumar Majumder (Dr Shyama Prasad Mukherjee&nbsp;&nbsp;&nbsp;International Institute of Information Technology, Naya Raipur); Deepika&nbsp;&nbsp;&nbsp;Gupta (Dr Shyama Prasad Mukherjee International Institute of Information&nbsp;&nbsp;&nbsp;Technology, Naya Raipu)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">118<\/td>\n    <td class=\"tg-hmp3\">Design&nbsp;&nbsp;&nbsp;of 3 bit\/cell NAND Memory Array based on Ferroelectric Field Effect&nbsp;&nbsp;&nbsp;Transistor<\/td>\n    <td class=\"tg-hmp3\">Albert&nbsp;&nbsp;&nbsp;Daimari (Tezpur University); Ankit Chakusaru Deori (Tezpur University); Arnab&nbsp;&nbsp;&nbsp;Ratna Pawe (Tezpur University); RATUL KUMAR BARUAH (Tezpur University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">212<\/td>\n    <td class=\"tg-0lax\">Design&nbsp;&nbsp;&nbsp;and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC&nbsp;&nbsp;&nbsp;Pixel<\/td>\n    <td class=\"tg-0lax\">Minal&nbsp;&nbsp;&nbsp;Bisen (Indian Institute of Technology Bhilai); Kapil Jainwal (Indian&nbsp;&nbsp;&nbsp;Institute of Technology Hyderabad); Nitin Khanna (Indian Institute of&nbsp;&nbsp;&nbsp;Technology Bhilai)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">290<\/td>\n    <td class=\"tg-hmp3\">Parallel-Series&nbsp;&nbsp;&nbsp;Diode-based Ring Amplifier for Switched Capacitor Circuits<\/td>\n    <td class=\"tg-hmp3\">Zainubia&nbsp;&nbsp;&nbsp;Zainubia (GCET Jammu); Bipul Kumar Singh (IIT Jammu); Manish Pundir (IIT&nbsp;&nbsp;&nbsp;Jammu); Subhash Chander Dubey (IIT Jammu); Ambika Prasad Shah (IIT Jammu)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">317<\/td>\n    <td class=\"tg-0lax\">A&nbsp;&nbsp;&nbsp;Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter&nbsp;&nbsp;&nbsp;and &lt;-255-dB FOMjitter<\/td>\n    <td class=\"tg-0lax\">ANSHUL&nbsp;&nbsp;&nbsp;VERMA (Indian Institute of Technology Roorkee); BISHNU PRASAD DAS (IIT&nbsp;&nbsp;&nbsp;Roorkee)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">428<\/td>\n    <td class=\"tg-hmp3\">An&nbsp;&nbsp;&nbsp;Integrated Multipurpose Low-Power Electrochemical Readout Interface with&nbsp;&nbsp;&nbsp;On-Chip Input Waveform Generator<\/td>\n    <td class=\"tg-hmp3\">Sayan&nbsp;&nbsp;&nbsp;Sarkar (HKUST)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">93<\/td>\n    <td class=\"tg-0lax\">Optimizing&nbsp;&nbsp;&nbsp;Medical Image Analysis: Leveraging Efficient Hardware and AI Algorithms<\/td>\n    <td class=\"tg-0lax\">Subhadeep&nbsp;&nbsp;&nbsp;Dolai (Liverpool John Moores University); Ekata Mitra (Portland State&nbsp;&nbsp;&nbsp;University); Hafizur Rahaman (Indian Institute of Engineering Science and&nbsp;&nbsp;&nbsp;Technology,Shibpur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">95<\/td>\n    <td class=\"tg-hmp3\">SpiCS-Net&nbsp;&nbsp;&nbsp;: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent&nbsp;&nbsp;&nbsp;Neural Networks<\/td>\n    <td class=\"tg-hmp3\">Manu&nbsp;&nbsp;&nbsp;Rathore (University of Tennessee); Garrett S. Rose (University of Tennessee)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">152<\/td>\n    <td class=\"tg-0lax\">Nano-watt&nbsp;&nbsp;&nbsp;Hyperdimensional Compute-in-Memory and Storage using Linear Floating-gate&nbsp;&nbsp;&nbsp;Injectors<\/td>\n    <td class=\"tg-0lax\">Darshit&nbsp;&nbsp;&nbsp;Mehta (Ginko Bioworks Inc.); Shantanu Chakrabartty (Washington University in&nbsp;&nbsp;&nbsp;St. Louis)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">253<\/td>\n    <td class=\"tg-hmp3\">Reconfigurable&nbsp;&nbsp;&nbsp;Processing-in-Memory Architecture for Data Intensive Applications<\/td>\n    <td class=\"tg-hmp3\">Sathwika&nbsp;&nbsp;&nbsp;Bavikadi (George Mason University); Purab Ranjan Sutradhar (Rochester&nbsp;&nbsp;&nbsp;Institute of Technology); Amlan Ganguly (Rochester Institute of Technology);&nbsp;&nbsp;&nbsp;Sai Manoj Pudukotai Dinakarrao (George Mason University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">339<\/td>\n    <td class=\"tg-0lax\">HARVEST:&nbsp;&nbsp;&nbsp;Towards Efficient Sparse DNN Accelerators using Programmable Thresholds<\/td>\n    <td class=\"tg-0lax\">Soumendu&nbsp;&nbsp;&nbsp;Ghosh (Intel Corporation); Shamik Kundu (University of Texas at Dallas);&nbsp;&nbsp;&nbsp;ARNAB RAHA (Intel Corporation); Deepak A. Mathaikutty (Intel Corporation);&nbsp;&nbsp;&nbsp;Vijay Raghunathan (Purdue University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">423<\/td>\n    <td class=\"tg-hmp3\">FP-BMAC:&nbsp;&nbsp;&nbsp;Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC<\/td>\n    <td class=\"tg-hmp3\">Saketh&nbsp;&nbsp;&nbsp;Gajawada (InternationalInstituteofInformationTechnologyBangalore); Aryan&nbsp;&nbsp;&nbsp;Gupta (IIT Gandhinagar); Kailash Prasad (Indian Institute of Technology&nbsp;&nbsp;&nbsp;Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">147<\/td>\n    <td class=\"tg-0lax\">Early&nbsp;&nbsp;&nbsp;RTL Exploration and Debug of Static DFT Verification in Mobile SoC and Edge&nbsp;&nbsp;&nbsp;AI Applications<\/td>\n    <td class=\"tg-0lax\">Vinod&nbsp;&nbsp;&nbsp;Viswanath (Real Intent, Inc.); Kanad Chakraborty (Real Intent)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">42<\/td>\n    <td class=\"tg-hmp3\">DRL-based&nbsp;&nbsp;&nbsp;Multi-Stream Scheduling of Inference Pipelines on Edge Devices<\/td>\n    <td class=\"tg-hmp3\">Danny&nbsp;&nbsp;&nbsp;Pereira (IIT Kharagpur); Sumana Ghosh (Indian Statistical Institute);&nbsp;&nbsp;&nbsp;Soumyajit Dey (IIT Kharagpur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">159<\/td>\n    <td class=\"tg-0lax\">A&nbsp;&nbsp;&nbsp;Pulse Oximeter And a Controller Designed For Automatic Regulation of Oxygen&nbsp;&nbsp;&nbsp;Concentrators<\/td>\n    <td class=\"tg-0lax\">DIBYA&nbsp;&nbsp;&nbsp;CHOWDHURY (Indian Institute of Technology Ropar); Shivdeep Shivdeep (Indian&nbsp;&nbsp;&nbsp;Institute of Technology Ropar); Devarshi Mrinal Das (Indian Institute of&nbsp;&nbsp;&nbsp;Technology Ropar)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">298<\/td>\n    <td class=\"tg-hmp3\">An&nbsp;&nbsp;&nbsp;Efficient Neural Network Controller for Autonomous Lane-Keeping Assist System<\/td>\n    <td class=\"tg-hmp3\">Debanjan&nbsp;&nbsp;&nbsp;Mallik (Jadavpur University); Sumana Ghosh (Indian Statistical Institute)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">151<\/td>\n    <td class=\"tg-0lax\">In-Memory&nbsp;&nbsp;&nbsp;SAT-Solver for Self-Verification of Programmable Memristive Architectures<\/td>\n    <td class=\"tg-0lax\">Fatemeh&nbsp;&nbsp;&nbsp;Shirinzadeh (University of Bremen); Arighna Deb (School of Electronics&nbsp;&nbsp;&nbsp;Engineering, KIIT University); Saeideh Shirinzadeh (German Research Center&nbsp;&nbsp;&nbsp;for Artificial Intelligence (DFKI)); Abhoy Kole (German Research Center for&nbsp;&nbsp;&nbsp;Artificial Intelligence (DFKI)); Kamalika Datta (University of Bremen); Rolf&nbsp;&nbsp;&nbsp;Drechsler (University of Bremen\/DFKI)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">215<\/td>\n    <td class=\"tg-hmp3\">Accelerating&nbsp;&nbsp;&nbsp;Fluid Loading in Sample Preparation with Fully Programmable Valve Arrays<\/td>\n    <td class=\"tg-hmp3\">Mohit&nbsp;&nbsp;&nbsp;Kumar (Havells); Abhik K. Khan (IIT Guwahati); Sudip Roy (IIT Roorkee);&nbsp;&nbsp;&nbsp;Krishnendu Chakrabarty (Arizona State University); Sukanta Bhattacharjee&nbsp;&nbsp;&nbsp;(Iitg)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">255<\/td>\n    <td class=\"tg-0lax\">Analysis&nbsp;&nbsp;&nbsp;of the Effects of Crosstalk Errors on Various Quantum Circuits<\/td>\n    <td class=\"tg-0lax\">Soumen&nbsp;&nbsp;&nbsp;Bajpayee (Indian Institute of Information Technology Kalyani); Imon Mukherjee&nbsp;&nbsp;&nbsp;(Indian Institute of Information Technology Kalyani)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">427<\/td>\n    <td class=\"tg-hmp3\">Hybrid&nbsp;&nbsp;&nbsp;CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant&nbsp;&nbsp;&nbsp;Applications<\/td>\n    <td class=\"tg-hmp3\">Monika&nbsp;&nbsp;&nbsp;Pokharia (Indian Institute of Technology, Gandhinagar); Kailash Prasad&nbsp;&nbsp;&nbsp;(Indian Institute of Technology Gandhinagar); Ravi Hegde (Indian Institute of&nbsp;&nbsp;&nbsp;Technology, Gandhinagar); Joycee Mekie (Indian Institute of Technology&nbsp;&nbsp;&nbsp;Gandhinagar)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">13<\/td>\n    <td class=\"tg-0lax\">Design&nbsp;&nbsp;&nbsp;for Trust utilizing Rareness Reduction<\/td>\n    <td class=\"tg-0lax\">Aruna&nbsp;&nbsp;&nbsp;Jayasena (University of Florida); Prabhat Mishra (University of Florida)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">193<\/td>\n    <td class=\"tg-hmp3\">KiD:&nbsp;&nbsp;&nbsp;A Hardware Design Framework Targeting Unified NTT Multiplication for&nbsp;&nbsp;&nbsp;CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA<\/td>\n    <td class=\"tg-hmp3\">Suraj&nbsp;&nbsp;&nbsp;Mandal (IIT Kanpur); Debapriya Basu Roy (Indian Institute of Technology&nbsp;&nbsp;&nbsp;Kanpur)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">195<\/td>\n    <td class=\"tg-0lax\">Pattern&nbsp;&nbsp;&nbsp;Based Synthetic Benchmark Generation for Hardware Security Applications<\/td>\n    <td class=\"tg-0lax\">Juneeth&nbsp;&nbsp;&nbsp;kumar Meka (University of Cincinnati); Satya AmarKant Marupureddy (University&nbsp;&nbsp;&nbsp;of Cincinnati); Ranga Vemuri (University of Cincinnati)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">203<\/td>\n    <td class=\"tg-hmp3\">Characteristic&nbsp;&nbsp;&nbsp;Exploitation of Programmable Delay Line Influenced Oscillator Circuit as&nbsp;&nbsp;&nbsp;Hardware Security Primitive<\/td>\n    <td class=\"tg-hmp3\">Sivaraman&nbsp;&nbsp;&nbsp;R (Research Scientist); Muralidaran D (Faculty); Muthaiah R (Professor);&nbsp;&nbsp;&nbsp;Shankar Sriram V S (Professor)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">232<\/td>\n    <td class=\"tg-0lax\">A&nbsp;&nbsp;&nbsp;High Throughput ASCON Architecture for Secure Edge IoT Devices<\/td>\n    <td class=\"tg-0lax\">Ayyappa&nbsp;&nbsp;&nbsp;Koppuravuri (International Institute of Information Technology Bangalore);&nbsp;&nbsp;&nbsp;Haribabu Pasupuleti (International Institute of Information Technology&nbsp;&nbsp;&nbsp;Bangalore); Sasirekha GVK (International Institute of Information Technology&nbsp;&nbsp;&nbsp;Bangalore); Jyotsna Bapat (International Institute of Information Technology&nbsp;&nbsp;&nbsp;Bangalore)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">354<\/td>\n    <td class=\"tg-hmp3\">Enhancing&nbsp;&nbsp;&nbsp;Output Corruption Through GSHE Switch Based Logic Encryption<\/td>\n    <td class=\"tg-hmp3\">Nikhil&nbsp;&nbsp;&nbsp;Saxena (University of Cincinnati); Ranga Vemuri (University of Cincinnati)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">414<\/td>\n    <td class=\"tg-0lax\">Evaluating&nbsp;&nbsp;&nbsp;the Robustness of Large scale eFPGA-based Hardware Redaction.<\/td>\n    <td class=\"tg-0lax\">Praveen&nbsp;&nbsp;&nbsp;Karmakar (IIT Guwahati); Marpina Bharani (IIT Guwahati); Chandan Karfa&nbsp;&nbsp;&nbsp;(Indian Institute of Technology Guwahati)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">416<\/td>\n    <td class=\"tg-hmp3\">Trojan&nbsp;&nbsp;&nbsp;Localization using Information Flow Tracking Properties in SoC Designs<\/td>\n    <td class=\"tg-hmp3\">Suriya&nbsp;&nbsp;&nbsp;Srinivasan (University of Cincinnati); Ranga Vemuri (University of&nbsp;&nbsp;&nbsp;Cincinnati)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">417<\/td>\n    <td class=\"tg-0lax\">Processing-in-Memory&nbsp;&nbsp;&nbsp;Architecture with Precision-Scaling for Malware Detection<\/td>\n    <td class=\"tg-0lax\">Sreenitha&nbsp;&nbsp;&nbsp;Kasarapu (George Mason University); Sathwika Bavikadi (Geroge Mason&nbsp;&nbsp;&nbsp;University); Sai Manoj Pudukotai Dinakarrao (George Mason University)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">422<\/td>\n    <td class=\"tg-hmp3\">SDR-PUF:&nbsp;&nbsp;&nbsp;Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space<\/td>\n    <td class=\"tg-hmp3\">Kailash&nbsp;&nbsp;&nbsp;Prasad (Indian Institute of Technology Gandhinagar); Neel Shah (Indian&nbsp;&nbsp;&nbsp;Institute of Technology Gandhinagar); Jinay Dagli (Indian Institute of&nbsp;&nbsp;&nbsp;Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology&nbsp;&nbsp;&nbsp;Gandhinagar)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">247<\/td>\n    <td class=\"tg-0lax\">Multi&nbsp;&nbsp;&nbsp;Port Register File Implementation Using SDP Approach For Optimized Area and&nbsp;&nbsp;&nbsp;Power<\/td>\n    <td class=\"tg-0lax\">vijay&nbsp;&nbsp;&nbsp;kumar vala (mediatek); priyanka gupta (mediatek)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">376<\/td>\n    <td class=\"tg-hmp3\">Broadband&nbsp;&nbsp;&nbsp;spectrum generation in Silicon nanocrystal-based dual-slot waveguide<\/td>\n    <td class=\"tg-hmp3\">SOMEN&nbsp;&nbsp;&nbsp;ADHIKARY (Senior Research Scholar); Ritesh Das (Junior Research Scholar);&nbsp;&nbsp;&nbsp;Mousumi Basu (Professor)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">7<\/td>\n    <td class=\"tg-0lax\">A&nbsp;&nbsp;&nbsp;Novel Approach to Control a DC-DC Converter Using its Empirical Physical&nbsp;&nbsp;&nbsp;Model<\/td>\n    <td class=\"tg-0lax\">Sushmita&nbsp;&nbsp;&nbsp;Ghosh (PhD Scholar, Indian Institute of Technology Delhi); Bidyut K.&nbsp;&nbsp;&nbsp;Bhattacharyya (Professor, School of Electrical and Computer Engineering,&nbsp;&nbsp;&nbsp;Georgia Institute of Technology)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">92<\/td>\n    <td class=\"tg-hmp3\">A&nbsp;&nbsp;&nbsp;novel controlled shutdown scheme for DC-DC converters enabling energy&nbsp;&nbsp;&nbsp;recycling<\/td>\n    <td class=\"tg-hmp3\">Anup&nbsp;&nbsp;&nbsp;Deka (Intel); Shobhit Tyagi (Intel)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">59<\/td>\n    <td class=\"tg-0lax\">Evolvable&nbsp;&nbsp;&nbsp;Hardware for Fault Mitigation in Control Circuits<\/td>\n    <td class=\"tg-0lax\">Deepanjali&nbsp;&nbsp;&nbsp;S (Indian Institute of Information technology Design and Manufacturing,&nbsp;&nbsp;&nbsp;Kancheepuram); Noor Mahammad Sk (Indian Institute of Information Technology&nbsp;&nbsp;&nbsp;Design and Manufacturing (IIITDM) Kancheepuram); Beautlin S (St.Joseph&#8217;s&nbsp;&nbsp;&nbsp;Institute of Technolology, Chennai)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">69<\/td>\n    <td class=\"tg-hmp3\">On&nbsp;&nbsp;&nbsp;Managing Test-Time, Power, and Layer Assignment in 3D SoCs with&nbsp;&nbsp;&nbsp;Built-In-Self-Repair Modules<\/td>\n    <td class=\"tg-hmp3\">SABYASACHEE&nbsp;&nbsp;&nbsp;BANERJEE (Asst. Prof.); Subhashis Majumder (Prof.); Bhargab B. Bhattacharya&nbsp;&nbsp;&nbsp;(Prof.)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-baqh\">202<\/td>\n    <td class=\"tg-0lax\">Structural&nbsp;&nbsp;&nbsp;Testing: Vmin Silicon Issues and Solutions<\/td>\n    <td class=\"tg-0lax\">Prashant&nbsp;&nbsp;&nbsp;Sonone (Mr); Pradeep R (Mr)<\/td>\n  <\/tr>\n  <tr>\n    <td class=\"tg-j0tj\">432<\/td>\n    <td class=\"tg-hmp3\">Genetic&nbsp;&nbsp;&nbsp;Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk&nbsp;&nbsp;&nbsp;Faults Among TSVs<\/td>\n    <td class=\"tg-hmp3\">Tanusree&nbsp;&nbsp;&nbsp;Kaibartta (Dr.); Hitarth Arora (IITISM); Debesh Kumar Das (Jadavpur&nbsp;&nbsp;&nbsp;University)<\/td>\n  <\/tr>\n<\/tbody>\n<\/table><\/div>\n\n<\/div><\/div><\/div><\/div><\/div>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"blocksy_meta":{"styles_descriptor":{"styles":{"desktop":"","tablet":"","mobile":""},"google_fonts":[],"version":5}},"_links":{"self":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/4108"}],"collection":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/comments?post=4108"}],"version-history":[{"count":2,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/4108\/revisions"}],"predecessor-version":[{"id":4358,"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/pages\/4108\/revisions\/4358"}],"wp:attachment":[{"href":"https:\/\/vlsid.org\/wp-json\/wp\/v2\/media?parent=4108"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}