We are excited to announce that submissions are now open for the Tape-Out Contest at VLSID 2027! This contest celebrates innovation and excellence in integrated circuit design in Academia.
Important Dates
- Submission Deadline: 30th September 2026
- Notification of Finalists: 10th November 2026
- Final Slides / Poster submission: 10th December 2026
Categories:
The contest has two categories:
- Digital Tape-Out: Designs implemented with digital logic.
- Analog Tape-Out: Circuits focused on analog, mixed-signal, or RF designs.
Eligibility:
Tape-Out is by an Academic Institution in India.
Students who have completed any digital or analog tape-out in the last two years (2025 or 2026) are welcome to participate.
Selection:
Five entries from Digital and five from Analog category will be shortlisted.
The shortlisted entries of this contest will be invited to attend VLSID 2027 and will be felicitated.
Submission Guidelines:
The template for submission can be downloaded from
- Maximum of TWO pages are allowed for submission.
- Participants should prepare a 2-minute video highlighting the features of the tape-out. The link to this video should be provided in the submission form.
- Select ‘Tapeout contest’ in the submission page, fill up the required details, and upload the pdf.
The submission (as a single pdf) should be done through the link: Submit here
For any questions, please contact tapeout@vlsid.org