40th International Conference on VLSI Design & 26th International Conference on Embedded Systems
📅 January 2–6, 2027
📍 Sheraton Grand Whitefield, Bengaluru, India
Artificial Intelligence to Physical Intelligence
From Compute to Cognition • From Silicon to Smart Systems
The 40th International Conference on VLSI Design and the 26th International Conference on Embedded Systems invites contributions to the User Design Track (UDT) to be held at the Sheraton Grand Whitefield, Bengaluru, India, from January 2–6, 2027.
As India’s premier conference on semiconductor design, electronic systems, and embedded technologies, this landmark edition provides a distinguished platform for experts from academia, industry, research laboratories, startups, and government organizations to present cutting-edge innovations, exchange ideas, foster collaborations, and shape the future of VLSI, semiconductor technologies, electronics manufacturing, and intelligent systems.
This year’s theme, “Artificial Intelligence to Physical Intelligence: From Compute to Cognition, From Silicon to Smart Systems,” reflects the rapid transformation of computing systems into intelligent, autonomous, and adaptive platforms capable of perceiving, reasoning, learning, and interacting with the physical world.
Achieving this vision requires innovation across the entire technology stack, from advanced semiconductor devices and chip design to embedded intelligence, connected systems, autonomous machines, and smart infrastructure.
User Design Track (UDT)
The User Design Track (UDT) provides a unique platform to showcase cutting-edge work happening in industry to a wider audience.
The unique slides-only format for UDT enables simplified and faster preparation for submission while encouraging the sharing of practical innovations, deployment experiences, lessons learned, work-in-progress developments, and late-breaking results.
We invite practitioners, researchers, architects, and design engineers from industry and academia to submit original presentations showcasing innovative methodologies, design flows, tools, case studies, industrial deployments, and measurable results across the semiconductor, electronics, embedded systems, and intelligent systems ecosystem.
Submissions should clearly articulate:
- The problem or challenge being addressed
- The technical innovation or contribution
- The design methodology, architecture, workflow, or implementation approach
- Quantifiable impact on productivity, performance, power, quality, reliability, scalability, manufacturability, cost, or time-to-market
- Key lessons learned and future directions
Contributions may describe novel use of commercial or internally developed tools, automation frameworks, AI-assisted design methodologies, IP integration strategies, silicon implementation experiences, physical design innovations, verification and validation techniques, manufacturing optimization, embedded and intelligent system deployments, hardware-software co-design approaches, or design trade-off studies.
The UDT Committee particularly encourages submissions that demonstrate how AI and intelligent technologies are driving the evolution from Compute to Cognition and from Silicon to Smart Systems.
Outstanding presentations showcasing exceptional originality and disruptive technical innovation will be rewarded.
Important Dates
- Final date of submission: 1st October, 2026
- Notification for Acceptance: 9th November, 2026
- Final Presentation Submission: 16th November, 2026
Topics of Interest
Submissions are invited on a wide range of topics, including but not limited to:
1. VLSI Chip Design
- AI-driven Electronic Design Automation (EDA) and design productivity
- Digital, analog, mixed-signal, RF and mm-wave design
- Low-power, high-performance and energy-efficient architectures
- Processor, SoC, chiplet and reconfigurable computing platforms
- Hardware accelerators for AI/ML and foundation models
- Design verification, validation, test and reliability
- Hardware security, trust and functional safety
- Advanced design methodologies for intelligent systems
2. Semiconductor Technologies & Devices
- Advanced semiconductor devices and process technologies
- Device modeling, simulation and reliability
- Beyond-CMOS and novel computing devices
- Photonics, optoelectronics and high-speed devices
- Advanced packaging, heterogeneous integration and chiplets
- 2.5D/3D integration and thermal management
- Power electronics and energy management solutions
- Semiconductor technologies enabling AI and physical intelligence
3. Semiconductor & Electronics Manufacturing
- Semiconductor fabrication and process integration
- Advanced packaging, assembly and test technologies
- PCB, electronics manufacturing and system integration
- Smart factories, Industry 4.0 and Industry 5.0
- AI, automation and digital manufacturing
- Yield enhancement, quality and process optimization
- Semiconductor equipment, ecosystem development and supply chains
- Sustainable and resilient manufacturing
4. Emerging Technologies
- Quantum computing and quantum systems
- Neuromorphic, brain-inspired and cognitive computing
- In-memory, near-memory and approximate computing
- Post-CMOS and next-generation computing paradigms
- Emerging memory technologies
- Heterogeneous integration and chiplet-based architectures
- Bio-inspired and genomics-on-chip technologies
- Future technologies for compute-to-cognition systems
5. Intelligent Systems
- Embedded systems and intelligent edge computing
- AIoT, IoT and cyber-physical systems
- Physical AI, robotics and autonomous systems
- Software-defined and connected vehicles
- Intelligent sensing, sensor fusion and digital twins
- Industrial automation and smart manufacturing systems
- Smart cities, infrastructure and sustainable systems
- Healthcare, wearables and human-centric intelligent applications
- Agentic AI, multi-agent systems and autonomous decision making
- Cognitive, adaptive and self-learning systems
Submission Categories
The User Design Track welcomes presentations describing:
- Industrial innovations and product deployments
- Work-in-progress (WIP) developments
- Late-breaking results
- Design and implementation experiences
- Case studies and lessons learned
- Best practices and design methodologies
- Technology demonstrations and prototypes
- Cross-domain innovations spanning silicon, software, systems, and AI
- Visionary perspectives on emerging technologies and future trends
Submission Requirements
Each submission must include:
1. Presentation Title
2. Abstract
100–200 words
3. Presenter Information
- Name
- Affiliation
- City, State, Country
- Email Address
Important: Presenters cannot be added after acceptance. Ensure all intended presenters are listed in the initial submission.
4. Presentation Deck
Six-Slide PowerPoint Presentation for technical review by the Program Committee.
Presentation Format
- Minimum of six (6) slides, Maximum of twelve (12) slides
- PowerPoint format only
- 16:9 aspect ratio
- Additional supporting information may be included in the speaker notes section
Blind Review Policy
To ensure a fair and unbiased review process:
- Do not include presenter names, affiliations, company names, acknowledgments, or logos anywhere in the submission deck.
- Company logos may appear only in the final accepted presentation.
- Non-compliant submissions may be disqualified.
Recommended Slide Structure
Slide 1 – Title
Provide a clear and concise title that communicates the main contribution of the work.
Slide 2 – Motivation
Introduce the design challenge and its significance. Describe the context in which the work is applied, identify existing limitations, and explain why the topic is relevant to the audience.
Slide 3 – Main Idea
Present the core technical contribution of the work. Topics may include:
- Novel methodologies or workflows
- Innovative use of design tools
- AI/ML-assisted design approaches
- Scalability techniques
- IP integration strategies
- Design optimization methods
- Manufacturing-aware design practices
Slide 4 – Additional Content
Use this slide to further demonstrate the value and uniqueness of the contribution. Examples include:
- Case studies
- Architectural insights
- Comparative analysis
- Design trade-off evaluation
- Deployment experiences
Slide 5 – Evidence
Provide quantitative or qualitative evidence supporting the effectiveness of the approach. Examples include:
- Productivity improvements
- Quality of Results (QoR) enhancements
- Runtime reductions
- Area, power, or performance gains
- Reduced design complexity
- Accelerated project schedules
Slide 6 – Summary
Summarize the key contributions, results, and overall impact. Clearly highlight the benefits and practical significance of the work.
Evaluation Criteria
Submissions will be evaluated based on:
- Technical merit and innovation
- Relevance to the design community
- Clarity of presentation
- Practical applicability
- Scalability and deployment potential
- Demonstrated results and measurable impact
Strong submissions should include clear evidence of benefits such as improved productivity, enhanced silicon quality, reduced design complexity, faster time-to-market, or other quantifiable outcomes.
Important Notice
Authors are responsible for obtaining all necessary legal, organizational, trademark, copyright, and publication approvals before submission.
Submission deadlines cannot be extended due to pending approvals.
Accepted Presentations
The six-slide submission serves as the basis for Program Committee review.
Accepted authors will be invited to prepare an expanded conference presentation consisting of a title slide, presenter slide, and approximately twelve content slides that build upon the accepted submission.
Questions?
For any questions, please email: