Conference Detailed Schedule

StartEndDuration8th Jan 2024
8:00 AM9:00 AM01:00Registration
Plenary Room
9:00 AM10:00 AM01:00Inauguration Ceremony
10:00 AM10:25 AM00:25Keynote1 – Sudhir Mallya, SVP Corporate Marketing, Alphawave Semi
10:25 AM10:50 AM00:25Keynote2 – Sandeep Bharathi, Chief Development Officer, Marvell
10:50 AM11:15 AM00:25Keynote3 – Aman Joshi, Vice President, Design Enablement & Automation, WD
11:15 AM11:55 AM00:40Tea Break and Inauguration of Exhibit Area

Track1 – Technical Track
Track2 – Technical Track
Track3 – Industry ForumTrack4 – Technical Track
Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS) Design
Track5 – User Design TrackTrack6 – Technical Track
Test, Verification, and Reliability
Track Chair:Track Chair:Track Chair:Track Chair:Track Chair:Track Chair:
11:55 AM12:15 PM00:20Paper ID: 39 MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy
Authors: Sashank Nishad (IntelTechnologyIndiaPvtLtd); Santanu Kundu (Intel Technology India Pvt. Ltd.); Nicolas Richaud (Intel Corporation); Mallikarjun S (IntelTechnologyIndiaPvtLtd); Manoranjan Prasad (IntelTechnologyIndiaPvtLtd); Lennart Renker (Intel Corporation)
Invited Talk
KeynoteInvited Talk 2 EmbeddedUDT PresentationInvited Talk
12:15 PM12:35 PM00:20Paper ID: 40 Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence
Authors: Manoranjan Prasad (Intel Technology India Pvt Ltd); Santanu Kundu (Intel Technology India Pvt. Ltd.); Lennart Renker (Intel Deutschland GmbH); Rakesh Ranjan (Intel Technology India Pvt Ltd)
Paper ID: 34 Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects
Authors: Jahnvi Singh (IIT Kharagpur); Nijwm Wary (IIT Bhubaneswar); Pradip Mandal (IIT Kharagpur)
KeynotePaper ID: 38 Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management
Authors: Swathi KumarVembu (NTU); Anupam Chattopadhyay (Nanyang Technological University); Sayandeep Saha (Indian Institute of Technology, Kharagpur)
UDT PresentationPaper ID: 56 Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization
Authors: B Naresh Kumar Reddy (NIT Tiruchirappalli); Yellapradaga Charan Krishna (Amrita Vishwa Vidyapeetham, Chennai); Poosarla Naga Satya Nitish (Amrita Vishwa Vidyapeetham, Chennai); Sita Devi Bharatula (Amrita Vishwa Vidyapeetham, Chennai)
12:35 PM12:55 PM00:20Paper ID: 175 Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement
Authors: Pooja Beniwal (Indraprastha Institute of Information Technology Delhi (IIIT-Delhi)); Sneh Saurabh (Indraprastha Institute of Information Technology)
Paper ID: 77 A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications
Authors: Chetan Mittal (International institute of information technology Hyderabad); Arnab Dey (IIITHyderabad); Anubhab Banerjee (International Institute of Information Technology,Hyderabad,India); Ashfakh Huluvallay (IIIT Hyderabad); Zia Abbas (International Institute of Information Technology (IIIT), Hyderabad)
KeynotePaper ID: 68 Long Short-Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring
Authors: Vijay Kumar (Indian Institute of Technology Delhi); Goldy Goldy (IIT Delhi); Kolin Paul (IIT Delhi); Mahesh Chowdhary (ST Microelectronics)
UDT PresentationPaper ID: 61 Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems
Authors: Raghavendra Kumar Sakali (IIITDM Kancheepuram); Sreehari Veeramachaneni (GRIET, Hyderabad); Noor Mahammad Sk (Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram)
12:55 PM1:15 PM00:20Paper ID: 286
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D
Authors: Sneha Lahiri (Dr. B. C. Roy Engineering College, Durgapur); Megha Kesh (Dr. B. C. Roy Engineering College, Durgapur); Rupsa Mandal (Dr. B. C. Roy Engineering College, Durgapur); Sovan Bhattacharya (Assistant Professor, Dr. B. C. Roy Engineering College, Durgapur); Anirban Bhattacharjee (KIT); Dola Sinha (Dr. B. C. Roy Engineering College, Durgapur); Chandan Bandyopadhyay (Dr. B. C. Roy Engineering College, Durgapur); Hafizur Rahaman (IIEST, Shibpur); Rolf Drechsler (university of bremen); Robert Wille (university of bremen)
Paper ID: 80 A 3nm Ultra-High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range
Authors: Sandipan Sinha (Mediatek Bangalore Pvt. Ltd.); Manish Trivedi (Mediatek Bangalore PVT LTD); Jaswinder Singh (Mediatek Bangalore PVT LTD); Sriharsha Enjapuri (Mediatek Bangalore PVT LTD); Deepesh Gujjar (Mediatek Bangalore PVT LTD); Ramesh Halli (Mediatek Bangalore PVT LTD); GiriShankar Gurumurthy (Mediatek Bangalore PVT LTD)
KeynotePaper ID: 217 MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures
Authors: Prakhar Diwan (Indian Institute of Technology Bombay); Suryakant Toraskar (Indian Institute of Technology Bombay); Varun Venkitaraman (Indian Institute of Technology Bombay); Nirmal Kumar Boran (National Institute of Technology Calicut); Chandramani Chaudhary (National Institute of Technology Calicut); Virendra Singh (Indian Institute of Technology Bombay)
UDT PresentationPaper ID: 124 LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore
Authors: Avishek Choudhury (New Alipore College, University of Calcutta); Brototi Mondal (Sammilani Mahavidyalaya); Kolin Paul (IIT Delhi); Biplab K. Sikdar (IIEST Shibpur)
1:15 PM1:35 PM00:20Paper ID: 436 A method to accurately simulate and detect transition time instants in piecewise linear SMPS circuits
Author: Saloni Tandon (Cadence Design Systems)
Paper ID: 88
Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications
Authors: Marichamy Divya (Department of Micro and Nanoelectronics, Vellore Institute of Technology); Siva Kumar Rapina (MSDG, Microchip Technology); Kumaravel S (Department of Micro and Nanoelectronics, Vellore Institute of Technology)
UDT PresentationPaper ID: 149 An Amalgamated Testability Measure Derived from Machine Intelligence
Authors: Soham Roy (Intel Corporation); Vishwani Agrawal (Auburn University)
1:35 PM2:35 PM01:00Lunch
2:35 PM3:00 PM00:25Keynote4 – Dr. Prith Banerjee, CTO, Ansys
3:00 PM3:25 PM00:25Keynote5 – Prof. Kaushik Roy, Purdue University
3:25 PM3:50 PM00:25Keynote6 – Industry Platinum Thales
3:50 PM4:15 PM00:25Keynote7 – Industry Platinum MicroChip
4:15 PM4:50 PM00:35Tea Break
Track7 – Technical Track
Emerging Computing and post-CMOS Technologies
Track8 – Technical Track
Track9 – Industry ForumTrack10 – Technical Track
Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS) Design
Track11 – User Design TrackTrack12 – Technical Track
Test, Verification, and Reliability
Track Chair:Track Chair:Track Chair:Track Chair:Track Chair:Track Chair:
4:50 PM5:10 PM00:20Paper ID: 89 Margin Propagation based Analog Soft-Gates for Probabilistic Computing
Authors: Ankita Nandi (Indian Institute of Science (IISc)); Pratik Kumar (Indian Institute of Science (IISc)); Shantanu Chakrabartty (Washington University in St. Louis); Chetan Singh Thakur (Indian Institute of Science (IISc))
Paper ID: 94 An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers.
Authors: Sumit Kumar (Indian Institute of Science); Dr. Gaurab Banerjee (Indian Institute of Science Bangalore)
KeynoteInvited Talk 6
UDT PresentationInvited Talk
5:10 PM5:30 PM00:20Paper ID: 183 Thermal Crosstalk Analysis in ReRAM
Passive Crossbar Arrays
Authors: Shubham Pande (IIT Madras); Bhaswar Chakrabarti (Indian Institute of Technology, Madras); Anjan Chakravorty (Indian Institute of Technology, Madras)
Paper ID: 97 A sub-µW Fully Integrated Compact CMOS Temperature Sensor for Passive RFID Applications
Authors: Jayaram chilaka (NITWarangal); Sreehari Rao Patri (NIT Warangal)
KeynotePaper ID: 283 ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems
Authors: Debabrata Senapati (IIT Guwahati); Dharmendra Maurya (CSE, IIT Guwahati); Arnab Sarkar (IIT Kharagpur); Chandan Karfa (Indian Institute of Technology Guwahati)
UDT PresentationPaper ID: 185 FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors
Authors: N. Vamshi Krishna (Birla Institute Of Technology & Science – Pilani, Hyderabad Campus); Anushka Chaudhary (Birla Institute Of Technology & Science – Pilani, Hyderabad Campus); Soumya J (Birla Institute Of Technology & Science – Pilani, Hyderabad Campus)
5:30 PM5:50 PM00:20Paper ID: 213 Optimized QAOA ansatz design for
two-body Hamiltonian problems
Authors: Ritajit Majumdar (Indian Statistical Institute); Debasmita Bhoumik (Indian Statistical Institute); Dhiraj Madan (IBM India Research Lab); Dhinakaran Vinayagamurthy (IBM India Research Lab); Shesha S. Raghunathan (IBM India Research Lab); Susmita SurKolay (INDIAN STATISTICAL INSTITUTE)
Paper ID: 99 A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals
Authors: Tamal Chowdhury (Indian Institute of Technology, Kharagpur); Pradip Mandal (Indian Institute of Technology, Kharagpur)
KeynotePaper ID: 321 Early Execution for Soft Error Detection
Authors: Raj Kumar Choudhary (Indian Institute of Technology Bombay); Janeel Patel (Indian Institute of Technology Bombay); Virendra Singh (Indian Institute of Technology Bombay)
UDT PresentationPaper ID: 207 Near Threshold at Gate based Test for Stuck-on Fault in Scan-chain Testing
Authors: R S Haripriya (Indian Institute of Technology, Tirupati); Soumitro Vyapari (Indian Institute of Technology, Tirupati); Jaynarayan Thakurdas Tudu (Indian Institute of Technology, Tirupati)
5:50 PM6:10 PM00:20Paper ID: 308 Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode
Authors: Kanupriya Varshney (IIT Ropar); Mani shankar Yadav (IIT Ropar); Devarshi Mrinal Das (IIT Ropar); Brajesh Rawat (IIT Ropar)
Paper ID: 104 A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator
Authors: Ishan Mishra (Indian Institute of Technology Bombay); Ganpat Anant Parulekar (Indian Institute of Technology Bombay); Shalabh Gupta (IIT Bombay)
Panel DiscussionPaper ID: 430 Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation On FPGA
Authors: Tamonash Bhattacharyya (Indian Institute of Engineering Science and Technology,Shibpur); Prasun Ghosal (IIEST, Shibpur); SONAM SINGH (Indraprastha Institute of Information Technology Delhi); Sujay Deb (IIIT Delhi)
UDT PresentationPaper ID: 327 X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology
Authors: Ashrith Harith (Siemens DISW); Nilanjan Mukherjee (Siemens Digital Industries Software); Yingdi Liu (Siemens Digital Industries Software); Jeffrey Mayer (Siemens Digital Industries Software)
6:10 PM6:30 PM00:20Paper ID: 358 Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches
Authors: Tamal Mandal (IIT Roorkee, India); Debraj Kundu (IIT Roorkee); Sudip Roy (IIT Roorkee)
Paper ID: 403 Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF Energy Harvester
Authors: Sumit Saha (Indian Institute of Technology Bombay); Prasad B Kanyaka (IIT Bombay); Mark Last (Ohio State University); Nima Ghalichechian (Georgia Tech University); V. Ramgopal Rao (IIT Bombay); Maryam Shojaei Baghini (Department of Electrical Engg., IIT-Bombay)
UDT PresentationPaper ID: 419 Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network
Authors: Subhadip Kundu (Qualcomm); Jais Abraham (Qualcomm)