Stay updated. Stay ahead.
Explore the full schedule of keynotes, technical sessions, panels, workshops, and networking events happening throughout VLSID 2026 in Pune.
VLSID 2026 – Detailed Agenda
Agenda.pdf
Registration
Collect your badges at the registration desk.
Time: 8 AM to 9 AM
Track Chair: Gaurav Goel
9.30 AM to 11 AM
Multi-Stacked More-than-Moore Emerging Devices
Prof. Sudeb Dasgupta, IIT Roorkee
11 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
HSIO Link – SERDES Design, Analysis and Adaptive Equalization Techniques
Ranjan Sahoo, NXP
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Industry-Driven Formal Verification: Techniques for Modern VLSI Design
Achutha Kirankumar, Synopsys
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.00 PM
Advancements in CPU Verification
Suraj Kamat, ARM
Track Chair: Hall 2 Chair
9.30 AM to 11 AM
Session for Hall 2
Speaker Name, Institute
Track Chair: Day 2 Chair
10.00 AM to 11.30 AM
Day 2 Session
Speaker Name, Institute
Track Chair: Day 2, Hall 2 Chair
10.00 AM to 11.30 AM
Day 2, Hall 2 Session
Speaker Name, Institute
Track Chair: Day 3 Chair
9.00 AM to 10.30 AM
Day 3 Session
Speaker Name, Institute
Track Chair: Day 3, Hall 2 Chair
9.00 AM to 10.30 AM
Day 3, Hall 2 Session
Speaker Name, Institute
Track Chair: Day 4 Chair
9.00 AM to 10.30 AM
Day 4 Session
Speaker Name, Institute
Track Chair: Day 4, Hall 2 Chair
9.00 AM to 10.30 AM
Day 4, Hall 2 Session
Speaker Name, Institute
Track Chair: Day 5 Chair
9.00 AM to 10.30 AM
Day 5 Session
Speaker Name, Institute
Track Chair: Day 5, Hall 2 Chair
9.00 AM to 10.30 AM
Day 5, Hall 2 Session
Speaker Name, Institute