Tutorial 1: Compound Semiconductor with particular focus on the increasing role of wide bandgap semiconductors in electronics
Speaker: Prof. Srabanti Chowdhury (Stanford)
We live in a very exciting time, often identified as the age of the fourth industrial revolution. With electrification at every level, we are witnessing the most significant transformation of transportation since the internal combustion engine. Smart devices, including appliances, equipment, and machinery, supported by the IoT, are becoming more intelligent and affordable. Robotics and autonomous vehicles promise to transform our lifestyles. Among all these new waves of technology, the idea of achieving a carbon-free energy system by 2050 is now more than a commitment and requires energy efficient electronics at every level.
Compound semiconductors in the form of III-Vs have enabled high speed electronics. A member of compound semiconductors known for its large energy bandgap and labeled as Wide-bandgap (WBG) semiconductors, present a pathway to enable much of these electronics with higher efficiency and newer functionalities, complementing Si. Semiconductor devices with higher power density have unprecedented value in both power and high frequency electronics. Reducing energy losses is not only critical for minimizing consumption of limited resources, but it also simultaneously enables compact and light weight solutions — the basis for a new industry offering increased performance at reduced system cost.
The success of gallium nitride has opened the door to other ultra-wide bandgap materials (e.g., Diamond, Aluminum Nitride and Gallium Oxide), presenting new area of research covering a wide spectrum from materials, physics, devices, and applications. In this talk I will focus on advancement of Wide bandgap materials and devices and walk you through some of our recent findings in electrical transport, as well as thermal management.
Willard and Inez Kerr Bell Faculty Scholar of Electrical Engineering (EE) at Stanford. Her research focuses on wideband gap (WBG) and ultra-wide bandgap (UWBG) materials and device engineering for energy efficient and compact system architecture for power electronics, and RF applications. Besides Gallium Nitride, her group is exploring Diamond for various active, and passive electronic applications, particularly thermal management. She received her M.S and PhD in Electrical Engineering from University of California, Santa Barbara.
She received the DARPA Young Faculty Award, NSF CAREER and AFOSR Young Investigator Program (YIP) in 2015. In 2016 she received the Young Scientist award at the International Symposium on Compound Semiconductors (ISCS). She is a senior member of IEEE and alumni of NAE Frontiers of Engineering. She received the Alfred P. Sloan fellowship in Physics in 2020. To date, her work has produced over 6 book chapters, 90 journal papers, 110 conference presentations, and over 30 patents (26 issued). She serves the program committee of several IEEE conferences including IRPS and VLSI Symposium, and the executive committee of IEDM.
Tutorial 1: Beyond 5G & 6G Wireless Communication
Speaker: Tushar Vrind (Samsung)
5G cellular technology is touted to bring the next level experience for the end-user. Some of the deployment of 5G has started in the last 2.5 years. While there is a lot of expectations of the future innovations that 5G can enable, researchers from both industry and academia have already started developing proof of concepts for novel enabling technologies for the next generation wireless communication, which is also referred to as Beyond 5G and 6G. It may hit the markets around 2028-2030. In this tutorial, the megatrends and requirements for beyond 5G and 6G communication, along with some enabling technologies will be introduced. Also, a deep dive into the recent research on topics like aerial communication and intelligent surfaces will be presented, along with their use cases and the benefits that they bring in the evolved network deployment.
Tushar Vrind is a Technical Director at Samsung Semiconductor India R&D (SSIR). He is a member of the Technical Ladder and past chair of the Communication & Connectivity Center of Excellence at SSIR. He has over 20 years of professional experience in wireless communication (2G to 5G) and embedded domain especially with the Exynos System on Chip (SoC) at Samsung Electronics. He has over 40+ applied patents and over 20+ grants worldwide in the areas of embedded systems and wireless protocols. He has co-authored over 30+ technical contributions, papers, and journals with 3GPP, IEEE. Tushar is a notable innovator, intrapreneur, and technology evangelist at SSIR. Tushar is also a Senior Member of IEEE and a member Executive Committee at IEEE Comsoc Bangalore Chapter. His research interests include wireless networking, cellular communication, medium access protocols, and resource allocation protocols, applications of the machine, and deep learning, and real-time operating systems. He holds a bachelor’s degree in Computer Engineering from Birla Institute of Technology, Mesra, India, and a Master of Science (Research) in Wireless Communication and Networks from the International Institute of Information Technology, Bangalore, India. He also participated in Stanford Ignite, a certification in Entrepreneurship and Innovation from the Graduate School of Business, Stanford University.
Tutorial 2: Heterogenous Integration (HI) using advanced packaging
Speakers: Arun Chandrasekhar & Rupesh Pothineni (Intel)
In this tutorial the presenters will cover the basics of Heterogeneous Integration (HI) starting with how Moore’s law has evolved and the different schemes of disaggregation (such as 2D, 2.5D & 3D). The tutorial will then move into the methods and techniques of design partition under disaggregation. This will be followed by the an overview of the advanced package technology offerings available at Intel & from OSATs along with a couple of case studies highlighting the complexities involved. Finally an overview of the various challenges facing us in advancing heterogeneous disaggregation in advanced packaging will be briefly discussed along with concluding remarks.
Arun Chandrasekhar is a Senior Packaging Engineer in the Data Centre Group at intel. He has been with Intel, Bangalore for ~18 years and has primarily been the architect & designer for multiple generation of Xeon server and Xe graphics packages. He is also an adjunct faculty in the Dept. of Electrical Systems Engg. at IISc, Bangalore. He holds a PhD from IMEC, Belgium, M.Tech from IISc, Bangalore & B.E from the College of Engg. Guindy, Chennai
Rupesh is a principal engineer in IoTG silicon development Group at intel. He has been with Intel for 18+ years and played leadership roles in the convergence of several SoC. His expertise is in floorplan tech readiness, HIP methodologies, layout Integration/verification, die disaggregation (Foveros, EMIB, Co-EMIB, OSAT) methodology development for Client, Server, IoTG products. He holds MS from Bits.
Tutorial 2: Meeting Signal Integrity & Reliability Requirements in Automotive SoC
Speaker: Murali Mohan Thota (Texas Instruments)
Signal integrity (SI) is the analysis, design and validation of the interconnects (chip, package, board) necessary for successful transmission of digital signals. Logic designers accustomed to working with binary logic can find the apparently imprecise, analog nature of SI particularly frustrating. Signal integrity engineering borrows ideas and practices from many branches of electrical engineering. This diversity can make SI seem mysterious, sometimes inconsistent and sometimes difficult to understand. In this talk, I will describe multiple signal integrity challenges in recent SOC designs and methods to overcome such challenges.
Murali has completed his B.Tech in Electronics and Communication Engineering from National Institute of Technology (NIT), Warangal and Joined TI post that. Murali has played significant role in TI India as part of the silicon design nearly over 21 years. He has spent most of his valuable time with C2000 product design in the timing closure, layout, pin-out and backend flow. He leads in architectural understanding, device layout, Reliability and SI analysis, IO design, die size vs. performance tradeoffs across silicon process nodes. He led more than 12 SOCs across silicon process nodes in TI.
Tutorial 3: Building a multi protocol wireless IoT Device
Speaker: Tarun Chaplot (Silicon Labs)
Most IoT devices need wireless connectivity, and increasingly, more than one wireless interface. A device using Bluetooth may need a Wi-Fi interface for ensuring operation using voice commands; a Wi-Fi device may need Bluetooth for provisioning; a Thread device may need Wi-Fi for connecting to the external world, and so on. Emerging IoT standards such as Matter from the Connectivity Standards Alliance define protocols for building interoperable IoT ecosystems that use a multitude of connectivity methods. This tutorial describes how wireless coexistence is built into the Silicon and how performance, power consumption, and interoperability are addressed. It then provides a hands-on experience of how IoT devices can be built using multi-protocol wireless modules taking IoT evaluation kits from Silicon Labs as an example. It covers device hardware design, software application on the device, and software on the cloud to complete the IoT solution.
Tarun Chaplot is an Applications Engineering Manager in Product Apps group for wireless NCP Modules group at Silicon Labs. He has an industry experience of over 14 Years in the field of embedded systems, WiFi and Bluetooth design. For the last 8 years he has been leading applications design of IoT for smart home and industrial applications and also keen on working on regulatory certifications for wireless modules. Tarun has a Masters in Electrical Engineering from National University of Singapore and a bachelors from University of Rajasthan, Jaipur. He is a great sports enthusiast and regularly plays Tennis to keep fit.
Tutorial 3: Security for Deep Learning – A Hardware Perspective
Speakers: Prof. Chip Hong Chang and Wang Si (NTU)
This tutorial will expose the security flaws and weaknesses that can impact the integrity and confidentiality of the deep learning hardware systems. Model integrity is a primary pillar for artificial intelligence (AI) trust to ensure that the system deliver and maintain the desirable quality of service and are free from unauthorized deliberate or inadvertent manipulation of the system throughout the lifetime of their deployment. A superior and well-trained deep neural network (DNN) classifier requires heavy investment on large labelled training dataset, human expertise and enormous computing power. It is not only an intellectual property (IP) of high market value but also consists of private and sensitive information. Unfortunately, existing DNN hardware implementations mainly focus on throughput and energy efficiency optimization, which can unintentionally introduce exploitable vulnerabilities. The situation is aggravated by the trend of deploying trained model on edge computing devices and leasing of AI models on cloud platform. This paradigm extends the attack surface and opens out an uncharted territory of security threats. Attack vectors such as rowhammer, fault injection and side-channel attacks bring serious challenges on cloud and endpoint devices. In view of the severe consequence of potentially degraded system quality, reliability and performance, as well as leakage of model IP and private data, some solutions have been proposed to enhance the security and trust of DNN hardware. These defenses include resilient hardware design to mitigate the attack impact, obfuscation methods to lock the model IP with specific key, operation masking to remove the dependencies between the processed data and side-channel signatures. This tutorial will focus on deployment threats, hardware attack vectors, reverse engineering of model parameters and inference data recovery on cloud and edge deep learning implementations. Recent efforts in developing resilient and trustworthy DNN hardware and their limitations are also presented and discussed.
Chip-Hong Chang received the B.Eng. (Hons.) degree from the National University of Singapore, in 1989, and the M. Eng. and Ph.D. degrees from Nanyang Technological University (NTU), Singapore, in 1993 and 1998, respectively. He served as a Technical Consultant in industry prior to joining the School of Electrical and Electronic Engineering (EEE), NTU, in 1999, where he is currently an Associate Professor. He holds joint appointments with the university as Assistant Chair of Alumni of the School of EEE from June 2008 to May 2014, Deputy Director of the Center for High Performance Embedded Systems from 2000 to 2011, and Program Director of the Center for Integrated Circuits and Systems from 2003 to 2009. He has coedited 5 books, 13 book chapters, more than 100 international journal papers (~80 are in IEEE Journals) and more than 180 refereed international conference papers. He has been well recognized for his research contributions in hardware security and trustable computing, low-power and fault-tolerant computing, residue number systems, and digital signal and image processing. He has delivered more than 50 keynotes, distinguished lectures, tutorials and invited seminars, including tutorials at the 2021 IEEE International System-on-Chip Conference (SOCC 2021), 2017 Asia and South Pacific Design Automation Conference (ASP-DAC 2017), the 2017 and 2021 IEEE International Symposium on Circuits and Systems (ISCAS 2017), and the Advance CMOS Technology Winter School (ACTS 2020).
Dr. Chang currently serves as the Senior Area Editor of IEEE Transactions on Information Forensic and Security (TIFS), and Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Very Large Scale Integration (TVLSI) Systems. He also served in past as the Associate Editor of the IEEE TIFS and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) from 2016 to 2019, IEEE Access from 2013 to 2019, IEEE TCAS-I from 2010 to 2013, Integration, the VLSI Journal from 2013 to 2015, Springer Journal of Hardware and System Security from 2016 to 2020 and Microelectronics Journal from 2014 to 2020. He also guest edited eight journal special issues including IEEE TCAS-I, IEEE Transactions on Dependable and Secure Computing (TDSC), IEEE TCAD and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), of which four are related to hardware security. He has served key appointments in the organizing and technical program committees of more than 60 international conferences (mostly IEEE), including the General Co-Chair of 2018 IEEE Asia-Pacific Conference on Circuits and Systems and the inaugural Workshop Chair and Steering Committee of the ACM CCS satellite workshop on Attacks and Solutions in Hardware Security. He is the 2018-2019 IEEE CASS Distinguished Lecturer, a Fellow of the IEEE, IET and AAIA.
Si Wang received both the B.Eng. degree (Hons.) and Ph.D. degree with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, in 2016 and 2021, respectively. She is currently working as a postdoctoral researcher in Professor Chip-Hong Chang’s research group. Her areas of research include hardware security, machine learning accelerator, machine learning security and so on. She has published 6 IEEE Journal and Conference papers, including Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), International Symposium on Circuits and Systems (ISCAS), Asian Hardware Oriented Security and Trust Symposium (AsianHOST) and International Conference on Solid-State and Integrated Circuit Technology (ICSICT). She ranked the 1st place and received the most popular poster video award in AI Research Student Conference (ARSC 2021) poster competition. She is an active member of IEEE society. She has served as a reviewer for ISCAS, AsianHOST, International Symposium on Hardware Oriented Security and Trust (HOST), Attacks and Solutions in Hardware Security (ASHES), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and etc. since 2017.
Tutorial 4: Logic Design of a RISC-V Microprocessor
Speaker: Rajat Gupta (Sensonics), Yogesh Tripathi
The Instruction set of a microprocessor uniquely describes its behaviour. It does not however uniquely specify the underlying or implicit structure of the Instruction Execution hardware for the specific instruction set. A methodology
will be described for the RISC V ISA that provides a systematic way to discover and optimise the underlying hardware.
Rajat Gupta is Co-founder and Director at Sensonics Devices Private Limited where he is researching solutions in medical electronics and personal health monitoring devices, embedded processors, and power efficient circuits for scientific computing.
Previously, he was Managing Director of Beceem Communications Pvt. Ltd., from 2004 to 2010, when Broadcom acquired Beceem. From 1999 to 2003, he was the Managing Director of Cypress Semiconductor India where he was responsible for the P&L of Indian operations. He also directed teams in emerging product areas, hiring as well as liaison with Industry and Academia.
Prior to Cypress, he was Vice President Technology Development at Arcus Technology Pvt. Ltd., Bangalore from 1992. At Arcus, Rajat developed embedded microprocessors, analog and mixed signal design technology in-house to enable Arcus to address the thenemerging mixed-signal IP market. He developed and successfully implemented a selfbootstrapped growth strategy for Arcus based on a high technology content IC design service model. Arcus was eventually acquired by Cypress in 1999.
Prior to Arcus, Rajat was Design Manager at Semi-Conductor Complex Ltd., Chandigarh (India). At SCL, for over 10 years, Rajat led design teams for the development of several ASICs for Defense, Space and other Government agencies.
Rajat obtained his B.E. (Electronics & Tele-Communications) from Calcutta University in 1980 and M.Tech (Integrated Electronics & Circuits) from IIT, Delhi in 1982. He is named inventor in 4 US Patents and is a senior member of IEEE.
Yogesh Tripathi is a RTL designer with 5+ years of experience. He holds a B.Tech degree in Electronics & Communication.
As part of the Sensonics team he helped build SR2300 an in-house embedded 32 bit RISC V core that includes a comprehensive POSIT based math compute engine along with corresponding custom instructions mapped to the RISC V ISA.
Previously he developed several FPGA based designs with VVDN.
Tutorial 4: AI in Security – A Potential to Make and Break a Secure Connected World
Speaker: Prof. Debdeep Mukhopadhyay (IIT KGP)
In this part of the talk, we provide a detailed overview on both the boon and bane of AI on Security. To be more specific we start with describing how Machine Learning (ML)/Deep Learning(DL) can be leveraged to perform advanced side channel attacks on cryptographic implementations. Subsequently, we present deep learning based methodologies for leakage assessment due to fault attacks on crypto-devices. We further present a state-of-the-art overview on the threats of machine learning in modeling Physically Unclonable Functions (PUFs), a promising hardware security primitive. Subsequently, we look at the opportunities from DL based methods in developing effective diagnostic tools for powerful malwares. We present case-studies on using Performance Counter based approaches in detecting menacing threats like ransomware and rowhammer attacks.
Prof. Debdeep Mukhopadhyay is currently a Professor at the Department of Computer Science and Engineering, IIT Kharagpur, India. At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Hardware Security. He had worked as, visiting scientist at NTU Singapore, visiting Associate Professor of NYU Shanghai, Assistant Professor at IIT Madras, and Visiting Researcher at NYU Tandon School of Engineering, USA. He holds a Ph.D., an M.S., and a B.Tech from IIT Kharagpur. His books include Fault Tolerant Architectures for Cryptography and Hardware Security (Springer), Cryptography and Network Security (Mc GrawHills), Hardware Security: Design, Threats, and Safeguards (CRC Press), and Timing Channels in Cryptography (Springer). He has written more than 250 papers in peer-reviewed conferences and journals and collaborated with several Indian/Foreign Organizations. He has been on the program committee and editorial boards of several top international conferences and journals. Prof. Mukhopadhyay is the recipient of the prestigious Shanti Swarup Bhatnagar Award 2021 for Science & Technology, and is a Fellow of the Indian National Academy of Engineers. He was awarded the DST Swarnajayanti Fellowship 2015-16, Data Security Council of India Award for Cyber Security Education, ASEM-DUO Fellowship, INSA Young Scientist award, INAE Young Engineer award, Associateship for the Indian Academy of Sciences. He was awarded the Outstanding Young Faculty fellowship from IIT Kharagpur, and the Techno-Inventor Best PhD award from the Indian Semiconductor Association. He has recently incubated a start-up on Hardware Security, ESP Pvt. Ltd. at IIT Kharagpur, and is a senior member of IEEE and ACM.
Manaar Alam is currently a Postdoctoral Associate at the Modern Microprocessors Architecture Laboratory, Center for Cyber Security – Research Institute, NYU Abu Dhabi, UAE. Manaar holds a PhD degree in Computer Science and Engineering from IIT Kharagpur, India. He received the prestigious IBM PhD Fellowship award during his PhD. He also holds an MTech degree from IIT Dhanbad, India, and a BTech degree from IEM Kolkata, India. He worked as a Visiting Research Assistant at NTU Singapore.
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