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Date Start End Session Chair Paper Title Author Affiliation
09-Jan 10:30 10:40 Namita Sharma,
Power aware DFT implementation techniques  Aniruddha Bhasale, Akhtar Tamboli, Bharat Londhe and Jay Shah  Seagate
10:40 10:50 Power Data Visualization Framework for Analytics & Modeling Efficiency  Dipankar Narendra Arya, Bharathi V and Shauvik Panda  Intel
10:50 11:00 Simulation Driven Analog Routing  Vishesh Kumar, Rajeev Singh and Akshita Mishra  Cadence Design Systems
11:00 11:10 Evolved Supply Set UPF Methodology  AMAN JAIN Seagate
11:10 11:20 Faster Memory Test/Repair Bring up on Mobile SoCs  ANJU GEORGE, Praveen Vijayan and Arvind Jain  Qualcomm
11:20 11:30 Real Time Pin Accessibility Validation While Developing Standard Cells Using Custom Compiler  Akshita Mishra, Prince Moudgil and Frederic Avellaneda  ST Microelectronics
09-Jan 12:10 12:20 Atul Bhargava,
ST Microelectronics
A 7mW, 3.3dB NF and 32dB gain 28GHz gm-boosted CG-CS LNA for 5G applications  Ritabrata Bhattacharya, Sankaran Aniruddhan, Vikas Aggarwal, Ashish Gupta and Taranjit Singh Kukal Cadence Design Systems
12:20 12:30 Comparison of Millimeter Quadrature VCOs for 28GHz 5G applications  Vikas Aggarwal, Ritabrata Bhattacharya, Ashish Gupta, Sankaran Aniruddhan and Taranjit Kukal Cadence Design Systems
12:30 12:40 PVT Compensated Pulsed Pre-Charge Write Assist for Wide-Range Reliable 6T-SRAM  Ashish Kumar, Srinivas Ravindran, Mohammad Aftab Alam and Gangaikondan S Visweswaran ST Microelectronics
12:40 12:50 Estimating Parasitic of Digital Top Routes in Analog and Mixed Signal IP  Gagan Rana and Vikas Chelani ST Microelectronics
12:50 13:00 Complex Logic Implementation by Soft Structured Block  Umesh Naik, Karthikeyan Natarajan and Rahul Bhankur  IBM
13:00 13:10 Robust Adaptive Read Scheme for 7nm Configuration SRAMs  Sree Rama KC Saraswatula, Santosh Yachareni, Shidong Zhou, Joy Chen, Teja Masina and Narendra Pulipati  Xilinx

Detail of User Design Track - Click here

Template of presentation - Click here

JECC, Jaipur

About VLSID Conference

VLSI Design Conference started as a simple idea in 1985: to sense the level of VLSI activities in India with a focus on engineering education & research. Over the years, the conference has grown equilaterally with a VLSI community that includes the likes of Multinational Industries, Academic contributors and Government bodies around the globe. With its global footprints VLSID is recognized as a 'Sister Conference' of Design Automation Conference. This conference is sponsored by VLSI Society of India (VSI).