User Design Track
Presentation
| Session -1 | Date & Time : Jan 6th, 2020, 4:00PM -6:00PM | Location : DIYA | Session Chair- Ayan Datta, Intel | |
| Paper Title | Authors | Track | Time Slot | Affliation |
| A Secure Audio Application using PRESENT Lightweight Cipher and its FPGA Implementation | Jai Gopal Pandey and Abhijit Karmakar | Front End Silicon Design | 4:00-4:20PM | CEERI |
| Iterative Optimizations to Minimize Global & Local Clock Skew using Quadratic Programming and Machine Learning | Prateek Pendyala and Vishant Gotra | Back End Silicon Design | 4:20-4:40PM | INTEL |
| Trusted Hardware Design with Online Monitoring DfTr Technique | sree ranjani | Front End Silicon Design | 4:40-5:00PM | IIT M |
| Improving low power implementation flow using special NOR isolation cells | AMAN JAIN | Back End Silicon Design | 5:00-5:20PM | |
| Silicon Proven FinFET based Design Optimization Techniques for Library Differentiation | Aroma Bhat, Arani Roy, Rajeela Deshpande, Mitesh Goyal, Abhishek Ghosh and Parvinder Kumar Rana | Transistor Level Design | 5:20-5:40PM | SAMSUNG |
| In-design DRC verification methodology | Sachin Shrivastava and Navit Rana | Back End Silicon Design | 5:40-6:00PM | CADENCE |
| Memento and certificate Honor | 6:00-6:10PM | |||
| Session -2 | Date & Time : Jan 7th, 2020, 10:45AM-12:45PM | Location : DIYA | Session Chair- Vishal Bansal, Cadence | |
| Low Power High-Density 6T-SRAM using Charge Recovery Hybrid Write Assist for Reliable Operation | Ashish Kumar and Mohammad Aftab Alam | Transistor Level Design | 10:45-11:05AM | ST Microelectronics |
| Latch Based Designs: Challenges and Solutions | Neelam Maniar, Hitesh Khandla, Shikha Subudhi, Vasudev Bangalore and Gopalakrishnan Sadagopan | Back End Silicon Design | 11:05-11:25AM | INTEL |
| Accelerating IR drop closure on incremental ECOs using Machine Learning | Prateek Pendyala and Akash Hegde | Back End Silicon Design | 11:25-11:45AM | INTEL |
| A compact PVT monitoring circuit with machine learning for power efficient SOC design | Koushik De, Abhishek Kumar Rai and Venkata Mallikarjuna | Front End Silicon Design | 11:45AM- 12:05PM | |
| Efficiency Booster Technology – A way to Near Threshold Design | Amit Chhabra | Transistor Level Design | 12:05-12:25PM | ARM |
| Memento and certificate Honor | 12:25:12:35PM | |||
Poster
| Title | Authors | Track | Affiliation | Date & time slot – 6th Jan 2020 | Location : Poser Display Area | Judges |
| Low power DSSS transmitter and its VLSI Implementation | jayasanthi R | Front End Silicon Design | 10:45-10:55AM | Manish Mathur, Suman Dwivedi | ||
| Hardware Accelerated Matrix Multiplication using a 400 MHz Systolic Array on a CPU+FPGA Platform | Reetinder Sidhu, Yashas N D, Vishal Rao, Rachna Aithal, Vennela Katasani, Sneha Rao and Vishal S | Back End Silicon Design | PES University | 10:55-11:05AM | ||
| Automated method to evaluate IP Compliance for SoC’s | Alok Chandra and Sandeep Prajapati | Back End Silicon Design | Averasemi | 11:05-11:15AM | ||
| Asynchronous Reset Verification with respect to State Machines for Algorithmic Designs | Kranthi kumar Gali, Ashwin Bhatt and Neelamekakannan Alagarsamy | Front End Silicon Design | Averasemi | 11:15-11:30AM | ||
| Physical Implementation of High Speed data bus for timing closure | Vidya Rao, Dennis Hafer and Kyle Schneider | Back End Silicon Design | Averasemi | 11:30-11:45AM | ||
| Active self-powered high efficiency rectifier with zero crossing detector for energy harvesting applications | Pooja Melinamani and Shivam Pandit | Embedded Systems and Software | Intel India | 11:45-11:55AM | ||
| Optimizing Compute (LSF) / EDA through Artificial Intelligence for expediting DV closure | Sriram K S and Somasunder Kattepura Sreenath | Embedded Systems and Software | SSIR | 11:55-12:05PM | ||
| Mementos and certificate Honor | 12:05-12:15PM | |||||
| A VLSI Implementation of the PRESENT Cipher for System-on-Chip Applications | Jai Gopal Pandey and Abhijit Karmakar | Front End Silicon Design | CSIR -Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India | 4:00-4:10PM | Shivraj Dharne, Preet Yadav | |
| EM-IR Analysis Driven Physical Design Methodology Development for On-chip Power Gating | Subhechcha Banerjee, Kushal Kamal, Suchibrata Das and Raghavendra Jagalur | Back End Silicon Design | Avera Semiconductor | 4:10-4:20PM | ||
| Ensuring Design Robustness on Full Memory IP using Sigma Amplification | Ashish Kumar and Rakesh Shenoy | Transistor Level Design | STMicroelectronics Pvt Ltd | 4:20-4:30PM | ||
| Modelling Scalable/Reusable Component for Handling Silicon Artefacts at High Speed I/F’s | Chethan G B, Sriram K S, Tapas Ranjan Jena and Somasunder Kattepura Sreenath | Front End Silicon Design | SSIR | 4:30-4:40PM | ||
| Power optimized solution to minimize oscillator startup failure | Vishnu K G J, Tamal Das, Avneesh Singh Verma and Sanjeeb Kumar Ghosh | Front End Silicon Design | Samsung Semiconductor India R&D Centre | 4:40-4:50PM | ||
| SoC Verification Techniques for IO-Coherency with MMU | Rajkumar Rajappa, Sooraj Sekhar and Baskar Rudhramurthy | Front End Silicon Design | Avera Semi | 4:50-5:00PM | ||
| Mementos and certificate Honor | 5:00-5:10PM | |||||
- Presenting author must register for main conference to present their paper/poster.
- In case already registered for main conference NO additional registration required for UDT.
- Poster printing will be taken care by conference organizing committee.
- Presenting author must be available next to his/her poster display at given time slot for presentation.