Conference Detailed Schedule
| Start | End | Duration | 8th Jan 2024 | |||||
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| 8:00 AM | 9:00 AM | 01:00 | Registration | |||||
| Plenary Room | ||||||||
| 9:00 AM | 10:00 AM | 01:00 | Inauguration Ceremony | |||||
| 10:00 AM | 10:25 AM | 00:25 | Keynote: Tittle: Pushing New Frontiers of Compute and Data Connectivity -The Rise of Custom Silicon and Chiplets in the AI era Sudhir Mallya, SVP Corporate Marketing, Alphawave Semi |
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| 10:25 AM | 10:50 AM | 00:25 | Keynote: Title: Innovations Driving Next Generation Accelerated Data Infrastructure Sandeep Bharathi, Chief Development Officer, Marvell |
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| 10:50 AM | 11:15 AM | 00:25 | Keynote: Title: Gen-erational Transformations in VLSI Engineering Aman Joshi, Vice President, Design Enablement & Automation, Western Digital |
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| 11:15 AM | 11:55 AM | 00:40 | Tea Break and Inauguration of Exhibit Area | |||||
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Ballroom1 | Ballroom2 | Ballroom3 | Ballroom4 | Ballroom5 | Ballroom6 | ||
| Track1 - Technical Track EDA |
Track2 - Technical Track AMS |
Track3 - Industry Forum | Track4 - Technical Track Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS) Design |
Track5 - User Design Track | Track6 - Technical Track Test, Verification, and Reliability |
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| Session Chair: Umesh Nair, AMD | Session Chair: Prof. Baibhab Chatterje, UFL | Session Chair: Navin Bishnoi, Marvell, India | Session Chair: Prof. Arindam Basu, Univ Hong Kong | Session Chair: Rituparna Mondal, MediaTek | Session Chair: Tapan J Chakraborty, CG | |||
| 11:55 AM | 12:15 PM | 00:20 | Paper ID: 39 MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy Authors: Sashank Nishad (IntelTechnologyIndiaPvtLtd); Santanu Kundu (Intel Technology India Pvt. Ltd.); Nicolas Richaud (Intel Corporation); Mallikarjun S (IntelTechnologyIndiaPvtLtd); Manoranjan Prasad (IntelTechnologyIndiaPvtLtd); Lennart Renker (Intel Corporation) |
Luminary Talk (Invited): Analog Design in VLSI: Blurring Boundaries in the Emerging Technology World Prof. Prajit Nandi, IIT KGP |
Leapfrogging into next decade of silicon to system Raghu Panicker, Kaynes |
Luminary Talk (Invited): Efficient AI Algorithm and Hardware Design with Neuromorphic Computing Prof. Priyadarshini Panda, Yale U |
UDT Paper ID : 8 A 4Ghz SRAM in 3nm with novel DFT scheme to improve at speed fault coverage. Authors : Sriharsha Enjapuri, Manish Trivedi, Deepesh Gujjar, Jaswinder Singh, Sandipan Sinha and Ramesh Halli (MediaTek India Technology Pvt. Ltd) UDT Paper ID : 21 FastMiner-Design and Implementation of FPGA accelerated Bitcoin Miner Authors : Mayank Kabra, Harshita Gupta, Asmita Zjigyasu and Madhav Rao (International Institute of Information Technology Bangalore) UDT Paper ID : 25 Process Mismatch Tolerant Adaptive Read Assist for SRAM using Replica Bias Control Authors : Ashish Kumar (STMicroelectronics India Pvt. Limited) UDT Paper ID : 43 Approximate CNN for Edge Computing Authors : Abhinav K, Nalesh S and Kala S (Indian Institute of Information Technology Kottayam, Kerala and Cochin University of Science and Technology, Kochi, Kerala) UDT Paper ID : 46 ATE Testing for Complex Memory at 7nm - DFT insights covering Peak-Power, Testing & Issues Authors : Jaykumar Goraseeya and Raj Gandhi (E Infochips Pvt. Ltd) UDT Paper ID : 51 System-Level Modeling for Real-Time DNN Inference on Edge Devices Authors : Tom Jose and Deepak Shankar (Mirabilis Design) |
Luminary Talk (Invited): Energy Efficient Architectures Prof. Virendra Singh, IIT Bombay |
| 12:15 PM | 12:35 PM | 00:20 | Paper ID: 40 Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence Authors: Manoranjan Prasad (Intel Technology India Pvt Ltd); Santanu Kundu (Intel Technology India Pvt. Ltd.); Lennart Renker (Intel Deutschland GmbH); Rakesh Ranjan (Intel Technology India Pvt Ltd) |
Paper ID: 34 Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects Authors: Jahnvi Singh (IIT Kharagpur); Nijwm Wary (IIT Bhubaneswar); Pradip Mandal (IIT Kharagpur) |
Research Driven Hardware Security – Landscape, Ecosystem and Opportunities Teja Chintalapati, DSCI |
Paper ID: 38 Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management Authors: Swathi KumarVembu (NTU); Anupam Chattopadhyay (Nanyang Technological University); Sayandeep Saha (Indian Institute of Technology, Kharagpur) |
Paper ID: 56 Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization Authors: B Naresh Kumar Reddy (NIT Tiruchirappalli); Yellapradaga Charan Krishna (Amrita Vishwa Vidyapeetham, Chennai); Poosarla Naga Satya Nitish (Amrita Vishwa Vidyapeetham, Chennai); Sita Devi Bharatula (Amrita Vishwa Vidyapeetham, Chennai) |
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| 12:35 PM | 12:55 PM | 00:20 | Paper ID: 175 Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement Authors: Pooja Beniwal (Indraprastha Institute of Information Technology Delhi (IIIT-Delhi)); Sneh Saurabh (Indraprastha Institute of Information Technology) |
Paper ID: 77 A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications Authors: Chetan Mittal (International institute of information technology Hyderabad); Arnab Dey (IIITHyderabad); Anubhab Banerjee (International Institute of Information Technology,Hyderabad,India); Ashfakh Huluvallay (IIIT Hyderabad); Zia Abbas (International Institute of Information Technology (IIIT), Hyderabad) |
Transforming semiconductor design using shift-left methodologies Umesh Sisodia, President & CEO, CircuitSutra |
Paper ID: 68 Long Short-Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring Authors: Vijay Kumar (Indian Institute of Technology Delhi); Goldy Goldy (IIT Delhi); Kolin Paul (IIT Delhi); Mahesh Chowdhary (ST Microelectronics) |
Paper ID: 61 Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems Authors: Raghavendra Kumar Sakali (IIITDM Kancheepuram); Sreehari Veeramachaneni (GRIET, Hyderabad); Noor Mahammad Sk (Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram) |
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| 12:55 PM | 1:15 PM | 00:20 | Paper ID: 286 A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D Authors: Sneha Lahiri (Dr. B. C. Roy Engineering College, Durgapur); Megha Kesh (Dr. B. C. Roy Engineering College, Durgapur); Rupsa Mandal (Dr. B. C. Roy Engineering College, Durgapur); Sovan Bhattacharya (Assistant Professor, Dr. B. C. Roy Engineering College, Durgapur); Anirban Bhattacharjee (KIT); Dola Sinha (Dr. B. C. Roy Engineering College, Durgapur); Chandan Bandyopadhyay (Dr. B. C. Roy Engineering College, Durgapur); Hafizur Rahaman (IIEST, Shibpur); Rolf Drechsler (university of bremen); Robert Wille (university of bremen) |
Paper ID: 80 A 3nm Ultra-High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range Authors: Sandipan Sinha (Mediatek Bangalore Pvt. Ltd.); Manish Trivedi (Mediatek Bangalore PVT LTD); Jaswinder Singh (Mediatek Bangalore PVT LTD); Sriharsha Enjapuri (Mediatek Bangalore PVT LTD); Deepesh Gujjar (Mediatek Bangalore PVT LTD); Ramesh Halli (Mediatek Bangalore PVT LTD); GiriShankar Gurumurthy (Mediatek Bangalore PVT LTD) |
Sustainable VLSI Designing: Innovations and Commitment Abhijith M V, Manager Application Engineering, Ansys |
Paper ID: 217 MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures Authors: Prakhar Diwan (Indian Institute of Technology Bombay); Suryakant Toraskar (Indian Institute of Technology Bombay); Varun Venkitaraman (Indian Institute of Technology Bombay); Nirmal Kumar Boran (National Institute of Technology Calicut); Chandramani Chaudhary (National Institute of Technology Calicut); Virendra Singh (Indian Institute of Technology Bombay) |
Paper ID: 124 LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore Authors: Avishek Choudhury (New Alipore College, University of Calcutta); Brototi Mondal (Sammilani Mahavidyalaya); Kolin Paul (IIT Delhi); Biplab K. Sikdar (IIEST Shibpur) |
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| 1:15 PM | 1:35 PM | 00:20 | Paper ID: 436 A method to accurately simulate and detect transition time instants in piecewise linear SMPS circuits Author: Saloni Tandon (Cadence Design Systems) |
Paper ID: 88 Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications Authors: Marichamy Divya (Department of Micro and Nanoelectronics, Vellore Institute of Technology); Siva Kumar Rapina (MSDG, Microchip Technology); Kumaravel S (Department of Micro and Nanoelectronics, Vellore Institute of Technology) |
Unlocking the Edge AI Potential: Development, Applications, and Lifecycle Management Sindhu Ramachandran, Director - Technology, CoE Leader for Artificial Intelligence, Quest Global |
Paper Id: 170 CAD Tools Pathway in Hardware Security Author: Sree Ranjani Rajendran (University of Florida); Farimah Farahmandi (University of Florida); Mark Tehranipoor (University of Florida) |
Paper ID: 149 An Amalgamated Testability Measure Derived from Machine Intelligence Authors: Soham Roy (Intel Corporation); Vishwani Agrawal (Auburn University) |
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| 1:35 PM | 2:35 PM | 01:00 | Lunch | |||||
| 2:35 PM | 3:00 PM | 00:25 | Keynote: Title: Design and Analysis of Multi-Die and 3D-IC Systems. Dr. Prith Banerjee, CTO, Ansys, USA |
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| 3:00 PM | 3:25 PM | 00:25 | Keynote: Title: Rethinking computing with Neuro-inspired Learning: Algorithms and Hardware Architecture Prof. Kaushik Roy, Purdue University |
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| 3:25 PM | 3:50 PM | 00:25 | Keynote: Title: How RISCV is impacting the Embedded world! Subhra Kanti Das, Head Research & Technology – Engineering Competence Centre, , Thales, India |
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| 3:50 PM | 4:15 PM | 00:25 | Keynote: Title: Microchip Technology Driving Market Trends and Skill Development Globally Srikanth Settikere, Vice President and Managing Director, Microchip India Development Centers |
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| 4:15 PM | 4:55 PM | 00:40 | Tea Break | |||||
| Track7 - Technical Track Emerging Computing and post-CMOS Technologies |
Track8 - Technical Track AMS |
Track9 - Industry Forum | Track10 - Technical Track Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS) Design |
Track11 - User Design Track | Track12 - Technical Track Test, Verification, and Reliability |
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| Session Chair: Prof. Bhargab B. Bhattacharya, ISI | Session Chair: Prof. Maryam Shojaei Baghini, IIT Bombay | Session Chair: Shiv Harit Mathur, Western Digital | Session Chair: Dr. Navneet Gupta, WDC | Session Chair: Ayan Dutta, WDC | Session Chair: Prof. Debesh Das, JU | |||
| 4:55 PM | 5:15 PM | 00:20 | Paper ID: 89 Margin Propagation based Analog Soft-Gates for Probabilistic Computing Authors: Ankita Nandi (Indian Institute of Science (IISc)); Pratik Kumar (Indian Institute of Science (IISc)); Shantanu Chakrabartty (Washington University in St. Louis); Chetan Singh Thakur (Indian Institute of Science (IISc)) |
Paper ID: 94 An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers. Authors: Sumit Kumar (Indian Institute of Science); Dr. Gaurab Banerjee (Indian Institute of Science Bangalore) |
Indigenization of Next Generation Electronic System Design using High Performance and Adaptive Computing Rohith Gopalakrishna, Country Sales Manager, AMD |
Luminary Talk (Invited): Computing-In-Memory for Edge Devices: Beyond DNN Acceleration Prof. Saibal Mukhopadhyay, Georgia Tech |
UDT Paper ID : 37 Low-cost, Power IR drop consideration methodology for high contact resistance in advanced technologies nodes for robust memory design and accurate characterization. Authors : Praveen Kumar Verma, Anuj Dhillon, Harshit Sharma and Vartul Sharma (STMicroelectronics India Pvt. Limited) UDT Paper ID : 40 CRVPGen : C-Random verification programs for Processor design validation Authors : Srinivasa Tipparaju, Rishna Patteri, Bijay Sharma and Karun Talari (MediaTek India Technology Pvt. Ltd) UDT Paper ID : 58 TinyML System for Detecting Life-Threatening Ventricular Arrhythmias Authors : Vipin Gautam, Sharad Sinha and Shitala Prasad (Indian Institute of Technology, Goa) UDT Paper ID : 78 SPARC - An intelligent autonomous flow for power switch Selection, Placement, Auto Routing and Connectivity optimization Authors : Subbash K P, Pardhu Pavan S and Vikash K T (Wester Digital) UDT Paper ID : 80 Robust Noise Immune Inverting Schmitt Trigger for Radiation Exposed Environment Authors : Aryan Kannaujiya and Ambika Prasad Shah (Indian Institute of Technology Jammu) UDT Paper ID : 83 Modulating Free Layer of Magnetic Tunnel Junction : A Novel Approach for Energy-Efficient Computing in Memory Authors : Alishaa B and Dr.Tripti S. Warrier (Cochin University of Science and Technology) UDT Paper ID : Efficient Workload Optimization for CPU-GPU Co-Design in Intelligent Cyber-Physical Systems Authors : Ashiqur Molla, Suraj Singh, Srijeeta Maity and Soumyajit Dey |
Luminary Talk (Invited): Reversible and Quantum Computing – Testability and Fault Tolerance Issues Prof. Indranil Sengupta, IIT KGP |
| 5:15 PM | 5:35 PM | 00:20 | Paper ID: 183 Thermal Crosstalk Analysis in ReRAM Passive Crossbar Arrays Authors: Shubham Pande (IIT Madras); Bhaswar Chakrabarti (Indian Institute of Technology, Madras); Anjan Chakravorty (Indian Institute of Technology, Madras) |
Paper ID: 97 A sub-µW Fully Integrated Compact CMOS Temperature Sensor for Passive RFID Applications Authors: Jayaram chilaka (NITWarangal); Sreehari Rao Patri (NIT Warangal) |
Achieving power efficiencies in GenAI era Sumit Goswami, Senior Director Of Engineering, Qualcomm |
Paper ID: 283 ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems Authors: Debabrata Senapati (IIT Guwahati); Dharmendra Maurya (CSE, IIT Guwahati); Arnab Sarkar (IIT Kharagpur); Chandan Karfa (Indian Institute of Technology Guwahati) |
Paper ID: 185 FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors Authors: N. Vamshi Krishna (Birla Institute Of Technology & Science - Pilani, Hyderabad Campus); Anushka Chaudhary (Birla Institute Of Technology & Science - Pilani, Hyderabad Campus); Soumya J (Birla Institute Of Technology & Science - Pilani, Hyderabad Campus) |
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| 5:35 PM | 5:55 PM | 00:20 | Paper ID: 213 Optimized QAOA ansatz design for two-body Hamiltonian problems Authors: Ritajit Majumdar (Indian Statistical Institute); Debasmita Bhoumik (Indian Statistical Institute); Dhiraj Madan (IBM India Research Lab); Dhinakaran Vinayagamurthy (IBM India Research Lab); Shesha S. Raghunathan (IBM India Research Lab); Susmita SurKolay (INDIAN STATISTICAL INSTITUTE) |
Paper ID: 99 A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals Authors: Tamal Chowdhury (Indian Institute of Technology, Kharagpur); Pradip Mandal (Indian Institute of Technology, Kharagpur) |
Identifying and Resolving multi-path Cyber-Physical System using a Reverse Engineering Platform Deepak Shankar, Vice President Technology, Mirabilis |
Paper ID: 321 Early Execution for Soft Error Detection Authors: Raj Kumar Choudhary (Indian Institute of Technology Bombay); Janeel Patel (Indian Institute of Technology Bombay); Virendra Singh (Indian Institute of Technology Bombay) |
Paper ID:207 Near Threshold at Gate based Test for Stuck-on Fault in Scan-chain Testing Authors: R S Haripriya (Indian Institute of Technology, Tirupati); Soumitro Vyapari (Indian Institute of Technology, Tirupati); Jaynarayan Thakurdas Tudu (Indian Institute of Technology, Tirupati) |
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| 5:55 PM | 6:15 PM | 00:20 | Paper ID: 308 Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode Authors: Kanupriya Varshney (IIT Ropar); Mani shankar Yadav (IIT Ropar); Devarshi Mrinal Das (IIT Ropar); Brajesh Rawat (IIT Ropar) |
Paper ID: 104 A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator Authors: Ishan Mishra (Indian Institute of Technology Bombay); Ganpat Anant Parulekar (Indian Institute of Technology Bombay); Shalabh Gupta (IIT Bombay) |
Integration in GaN: Challenges and Prospects - An Examination of Lateral Gallium Nitride (GaN) Power Devices After a Decade of Development Syed Asif Eqbal, Tagore Tech |
Paper ID: 430 Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation On FPGA Authors: Tamonash Bhattacharyya (Indian Institute of Engineering Science and Technology,Shibpur); Prasun Ghosal (IIEST, Shibpur); SONAM SINGH (Indraprastha Institute of Information Technology Delhi); Sujay Deb (IIIT Delhi) |
Paper ID: 327 X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology Authors: Ashrith Harith (Siemens DISW); Nilanjan Mukherjee (Siemens Digital Industries Software); Yingdi Liu (Siemens Digital Industries Software); Jeffrey Mayer (Siemens Digital Industries Software) |
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| 6:15 PM | 6:35 PM | 00:20 | Paper ID: 358 Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches Authors: Tamal Mandal (IIT Roorkee, India); Debraj Kundu (IIT Roorkee); Sudip Roy (IIT Roorkee) |
Paper ID: 403 Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF Energy Harvester Authors: Sumit Saha (Indian Institute of Technology Bombay); Prasad B Kanyaka (IIT Bombay); Mark Last (Ohio State University); Nima Ghalichechian (Georgia Tech University); V. Ramgopal Rao (IIT Bombay); Maryam Shojaei Baghini (Department of Electrical Engg., IIT-Bombay) |
Neuromorphic processors - Introducing the domain, the opportunities, the innovations Uma Mahesh, Co-Founder, Innatera Nanosystems |
Paper ID: 419 Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network Authors: Subhadip Kundu (Qualcomm); Jais Abraham (Qualcomm) |
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| Start | End | Duration | 9th Jan 2024 | |||||
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| 8:00 AM | 9:00 AM | 01:00 | Registration | |||||
| Plenary Room | ||||||||
| 9:00 AM | 9:25 AM | 00:25 | Keynote: Title: Charting the AI-Powered Transformation in the Semiconductor Industry Sivakumar P R, CEO of Maven Silicon |
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| 9:25 AM | 9:50 AM | 00:25 | Keynote: Title: Engineer a Smarter Future - Faster & Together Ruchir Dixit, Vice President & Country Manager, Siemens EDA |
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| 9:50 AM | 10:15 AM | 00:25 | Keynote: Tittle: Enabling the Next Generation of VLSI Designs with Silicon Lifecycle Management and AI Driven Test Thryambak Chandilya, Group Director, Hardware Analytics and Test, Synopsys |
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| 10:15 AM | 10:40 AM | 00:25 | Keynote: Title: Microelectronics Security in the Era of Global Semiconductor Initiatives Prof. Mark M. Tehranipoor, University of Florida, USA |
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| 10:40 AM | 11:20 AM | 00:40 | Tea Break and Inauguration of Design Contest and Poster Area | |||||
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Ballroom1 | Ballroom2 | Ballroom3 | Ballroom4 | Ballroom5 | Ballroom6 | ||
| Track 13 - Technical Track Hardware Security and Emerging Technologies |
Track 14 - Design Contest Chip Design |
Track 15 - Industry Forum | Track 16 - Technical Track Autonomous Systems Design |
Track 17 - WIE | Track18 - Poster | |||
| Session Chair: Prof. Ujjawal Guin, Auburn University |
Session Chair: Prof. Maryam Shojaei Baghini, IIT Bombay | Session Chair: Sudipto Das, Quest Global | Session Chair: Prof. Arnab Sarkar, IIT KGP | Session Chair: Prof. Usha Meheta, Nirma Univ | Session Chair: | |||
| 11:20 AM | 11:40 AM | 00:20 | Luminary Talk (Invited): Compiler Assisted Automated Security Countermeasures for Embedded Crypto-Software Prof. Chester Rebeiro, IIT Madras |
A Scalable Single-Inductor Multiple-Output DC-DC Converter With Constant Charge-Transfer and Power-up Sequencing for IoT Applications Aditi Chakraborty, Ashish Kumar Jha, Dr. Anupama Deo, Dr. Ashis Maity, Prof. Amit Patra (IIT Kharagpur) |
Reimagining AI Developement for India Dr. Biswajit Patra, Krutrim |
Luminary Talk (Invited): Challenges in Designing Safe Autonomous Systems Prof. Samarjit Chakraborty, UNC Chapel Hill |
Keynote: Mrs Sunita Verma, Group Coordinator, R&D MeitY |
Poster |
| 11:40 AM | 12:00 PM | 00:20 | Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG Author: Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Anupam Chattopadhyay, Vikas Rana Experimental Validation of MemristorAided Logic Using 1T1R TaOx RRAM Crossbar Array Author: Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, André Zambanini, Dennis Nielinger, Sachin Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana Designing Hash and Encryption Engines using Quantum Computing Author: Suryansh Upadhyay, Rupshali Roy, Swaroop Ghosh Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture Author: Noa Aflalo, Eilam Yalon, and Shahar Kvatinsky |
A 100 MHz Bandwidth, 73.5dB SNDR, Filtering Continuous-Time Pipelined ADC in 65nm CMOS Shanthi Pavan, Nishanth Basavaraj and Saravana Manivannan (IIT Madras) |
Scaling the Generative AI infrastructure with Accelerated Optical and Copper Connectivity Lenin Patra, Vice President & CTO - PHY, Marvell |
Certifiable and Efficient Autonomous Cyber-Physical Systems Design Author:Shengjie Xu (UNC Chapel Hill, USA), Clara Hobbs (UNC Chapel Hill, USA), Bineet Ghosh (University of Alabama, USA), Parasara Sridhar Duggirala (UNC Chapel Hill, USA), and Samarjit Chakraborty (UNC Chapel Hill, USA) Autonomous Automotives on the Edge Author: Kaustabha Ray (IBM Research India and ISI), Ansuman Banerjee (ISI) Certifying Learning-Enabled Autonomous Cyber Physical Systems Author: Suraj Singh, Somnath Hazra, Sumanta Dey and Soumyajit Dey (IIT Kharagpur) SMT-based Control Safety Property Checking in Cyber-Physical Systems under Timing Uncertainties Author: Anand Yeolekar (TCS Research Pune and TUM Germany), Ravindra Metta (TCS Research Pune and TUM Germany) and Samarjit Chakraborty (UNC Chapel Hill, USA) Paper Id 220 Logic locking emulator on FPGA: A conceptual view Author: Manjith Baby Sarojam Chellam (Assistant Professor); Ramasubramanian Natarajan (Professor, NIT Tiruchirappalli); Nagi Naganathan (Microsoft, Raleigh NC, USA) |
Keynote: Dr. Kanchana Bhaaskaran V. S ; Vice - Chancellor & Pro-Vice Chancellor, Chennai Campus |
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| 12:00 PM | 12:20 PM | 00:20 | ARYABHAT (Analog Reconfigurable Technology And Bias-scalable Hardware for AI Tasks) Prof. Chetan Singh Thakur, Prof. Shantanu Chakrabartty, Pratik Kumar, Ankita Nandi, Kurupati Sai Pruthvi Teja (IISc Bangalore) |
VLSI: Will it be unprecedented with AI? Moderator| Sudipto Das, Quest Global Member| Sridhar H Rangarajan, Group Director - Engineering, Cadence Member| Bhanu Prakash, Embedded Solutions Manager, Microchip Member| Biswadeep Chatterjee, Associate Vice President, HCL Member| Venkatesh Duraisamy, Director, Product Design Engineering, Western Digital Member| Avinash Sekhar, Alphawave Member| Praful Pai, Manager - ECE, Mathworks |
Keynote: Seema Malhotra, Director, Physical Design Engg, Western Digital |
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| 12:20 PM | 12:40 PM | 00:20 | Digitally Intensive Programmable Sub-sampling Mixer-First Receiver RF front-ends for IEEE 802.15.4 IoT Applications. Raviteja Kammari, Rakesh Varma Rena, Dr. Vijay Shankar Pasupureddi (IIT Bhubaneswar) |
Panel Discussion: Moderator: Prof Ankita Pramanik, IIEST, Shibpur Member| Anasua Bhowmik, AMD Member| Viji Ranganna, Google Member|Seema Jain, Western Digital Member| Ruchi Jhari, Cadence |
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| 12:40 PM | 1:00 PM | 00:20 | Signal-Strength Detector Based on CMOS-Inverter Supply Current Pranav Kumar, Nagendra Krishnapura IIT Madras |
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| 1:00 PM | 2:00 PM | 01:00 | Lunch | |||||
| 2:00 PM | 2:25 PM | 00:25 | Keynote: Title: AI: Creating Tomorrow's World Sanjay Churiwala, Corporate Vice President, AMD |
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| 2:25 PM | 2:50 PM | 00:25 | Keynote: Title: A Comprehensive Journey Through Holistic GenAI Innovations Srini Maddali, Senior Vice President Engineering, Qualcomm |
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| 2:50 PM | 3:15 PM | 00:25 | Keynote: Title: Scalable SoC/SiP & AI Integration in Automotive HPC Prof. Juergen Becker, Karlsruhe Institute of Technology, Germany |
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| 3:15 PM | 3:55 PM | 00:40 | Academic Panel Discussion: Next-gen Chip Designers for the AI-driven Semiconductor Industry Moderator: Sivakumar P R, CEO of Maven Silicon Member| Prof. Partha Pratim Das, Director, Center for Data Science and Analytics, Ashoka University Member | Prof. Kaushik Roy, Purdue University Member | Sanjay Churiwala, Corporate Vice President, AMD Member | Prof. V.Ramgopal Rao, Vice-Chancellor, BITS |
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| 3:55 PM | 4:25 PM | 00:30 | Tea Break | |||||
| Plenary Room | ||||||||
| Track19 - Technical Track AI/ML in VLSI |
Track20- Design Contest Embedded Systems |
Track21 - Startup Forum Keynote | Track22 - Student Research Forum/ PhD Forum |
Track23 - Academic Sponsorship Talk | Track24 - Poster | |||
| Session Chair: Prof. Soumyajit Dey, IIT KGP |
Session Chair: Arpan Pal, TCS, Kolkata |
Session Chair: Prof. Gaurab banerjee, IISc Bangalore | Session Chair: Prof. Manodipan Sahoo, IIT Dhanbad & Prof. Debprasad Das, Central University, Assam |
Session Chair: | Session Chair: | |||
| 4:25 PM | 4:45 PM | 00:20 | Luminary Talk (Invited): Title: Bridging Worlds: VLSI & Quantum Electronics Dr. S D Sudarsan, Executive Director, CDAC |
AI-Enabled Detection of Autism Spectrum Disorder (ASD) and Therapy Using Emotional State Recognition Author: Asmita Zjigyasu, Shivangi, Nancy Gupta, Yash Dharmesh Mogal, Dr. Nanditha Rao, IIIT Bangalore Gait Phase Identification using Wearable Sensors for Physiotherapy Assistance Author: Rufyid-u-Nissa, Khalid Shaikh, Mohin Shaikh, Arhum Alam, IIT Bombay , AMU ML model to predict the angle of the lower limb and abnormal motion during sit-to-stand motion Author: Nitheezkant R, Aamod B K , Anshul M , Anmol Shetty, Dr. Madhav Rao, IIIT Bangalore Audio Keyword Detection for hands-free control in Automobiles Author: Ashwin Rajesh, Venkata Likhith L , IISc Bangalore , IIIT Kancheepuram AUTOMATIC MODULATION CLASSIFICATION (AMC) USING MR-CNN ON THE STM32L4 series B-L475E-IOT01A Discovery kit Author: Disha Lad, Harshal Patel, Dev Desai, Riya Gupta, SVNIT, Surat |
Translational Research: The Lab to Fab Journey, Dr. Gaurab Banerjee, IISc |
SRF & PhD Presentation | Academic Sponsor-VIT | Poster |
| 4:45 PM | 5:05 PM | 00:20 | Paper Id 366 FLIP: An Artificial Neural Network-based Post-routing Incremental Placer Author: Pranav Jain (Indraprastha Institute of Information Technology Delhi (IIITD)); Gagandeep (Indraprastha Institute of Information Technology Delhi (IIITD)); Sneh Saurabh (Indraprastha Institute of Information Technology) Paper Id 393 Machine Learning based Waveform Predictions using Discrete Wavelet Transform for Automated Verification of Analog and Mixed Signal Integrated Circuits Author: Dhurga Devi J (College of Engineering Guindy, Anna University); Selvi Ravindran (Anna University); Bama Srinivasan (Anna University); Lakshmanan Balasubramanian (Texas Instruments (India) Pvt. Ltd.); Ranjani Parthasarathi (CEG Campus, Anna University); Ramakrishna P V (CEG Campus, Anna University) Paper Id 412 Reinforcement Learning based Droplet Routing Technique in Hexagonal Digital Microfluidic Biochips using Dueling Network Author: Amartya Dutta (B. P. Poddar Institute of Management and Technology, Kolkata); Riya Majumder (Netaji Subhash Engineering College); Rajat Kumar Pal (University of Calcutta) Paper Id 205 SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking Author: Jugal Gandhi (AcSIR at CSIR-CEERI); Rishi Agarwal (BITS Pilani); Anish Mall (BITS Pilani); Diksha Shekhawat (AcSIR at CSIR-CEERI); M. Santosh (CSIR-CEERI); Jai Gopal Pandey (CSIR-CEERI) |
The role of Chip Incubator in Indian Ecosystem Dr. Siva Vanjari, FabCI/IITH |
Academic Sponsor- Vignan | |||
| 5:05 PM | 5:25 PM | 00:20 | Current Government Initiatives Shri Nishit Gupta, Meity, GOI |
Academic Sponsor-UEM | ||||
| 5:25 PM | 5:45 PM | 00:20 | Fundrising for the Startup Journey Mr. Avelo Roy, Kolkata Ventures |
Academic Sponsor - Supreme Knowledge Foundation Academic Sponsor - Netaji Subhas Engineering College |
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| Networking Break | ||||||||
| 6:15 PM | 6:40 PM | 00:25 | Banquet Talk: Title: Analog Spiking Processors for Intelligent Sensing Dr. Aditya Dalakoti, Principal Engineering Manager, Innatera Nanosystems |
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| 6:40 PM | 7:10 PM | 00:30 | Award Ceremony | |||||
| 7:10 PM | 7:35 PM | 00:25 | Banquet Talk: Title: Open Platform for the Embodied AI Era Prof. Luca Benini, ETH Zürich, Switzerland |
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| 7:35 PM | 7:45 PM | 00:10 | Address by General Chair VLSID 2025 | |||||
| 7:45 PM | 8:45 PM | 01:00 | Cultural Program | |||||
| 8:30 PM | 10:00 PM | 01:30 | Banquet Dinner | |||||
| Start | End | Duration | 10th Jan 2024 | |||||
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| 8:00 AM | 9:00 AM | 01:00 | Registration | |||||
| Plenary Room | ||||||||
| 9:00 AM | 9:25 AM | 00:25 | Keynote: Title: Polynomial Formal Verification for Ensuing Processor Correctness Prof. Rolf Drechsler, University of Bremen, Germany |
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| 9:25 AM | 10:10 AM | 00:45 | Panel Discussion: Government Initiatives and Efforts for Semiconductors & VLSI Design Moderator| Chitra Hariharan, Secretary, VLSI Society of India Member | Rajeev Kumar, Principal Secretary, Dept of IT and Electronics, Govt of WB Member | Debashis Dutta, Executive Vice President and Chief Scientist at Reliance Jio Infocom Limited, Former Group Coordinator R&D, MeitY Member | Aditya Kumar Sinha, Director at C-DAC Patna & C-DAC Kolkata |
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| 10:10 AM | 10:35 AM | 00:25 | Fireside Chat: Future of Research and Technology Development for Semiconductor Technology & Chip Design Moderator| Dr. Satya Gupta, President, VLSI Society of India Member| Prof. Subhasish Mitra, Stanford University, USA |
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| 10:35 AM | 10:50 AM | 00:15 | Talk: WEBEL@50 - a new beginning Sanjay Kumar Das, MD, WEBEL |
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| 10:50 AM | 11:20 AM | 00:30 | Tea Break | |||||
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Ballroom1 | Ballroom2 | Ballroom3 | Ballroom4 | Ballroom5 | Ballroom6 | ||
| Track25 - Technical Track AI/ ML |
Track26 - Technical Track AMS |
Track27 - Startup Forum | Track28 - Technical Track Hardware Security |
Track29 - Technical Track Advanced Process/Material, Device Design and Modelling |
Track30 - Low-power Digital Systems |
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| Session Chair: Prof. Shanti Prasad Maity, IIEST | Session Chair: Prof. Soumya Pandit, CU | Session Chair: Atul Prakash Agarwal, Apt Software Avenues Pvt. Ltd. | Session Chair: Prof. Subhajit Das, SR Univ | Session Chair: Prof. Sanatan Chattopadhyay, CU | Session Chair: Prof. Indrajit Chakraborty, IIT KGP | |||
| 11:20 AM | 11:40 AM | 00:20 | Luminary Talk (Invited): Challenges of Computing System Design in the Generative AI Era Krishnan Kailas, IBM Thomas J. Watson Research Center |
Luminary Talk (Invited): Transmission-Line-Based Phase Shifters for Millimeter Wave Systems Prof. Sankaran Aniruddhan, IIT Madras |
Title: Startup Intellectual Property (IPR) Awareness Souvik Basu, Director (Program Management), Qualcomm |
Luminary Talk (Invited): Is your Compiler Secure? Prof. Chandan Karfa, IITG |
Luminary Talk (Invited): High-Frequency Characterization and Modeling of Low and High Voltage FinFETs for RF SoCs Prof. Yogesh S. Chauhan, IIT Kanpur |
Luminary Talk (Invited): An overview of High Bandwidth Memory (HBM) - the cortex of today's Generative AI hardware Venkatraghavan Bringivijayraghavan, Senior Director, Micron |
| 11:40 AM | 12:00 PM | 00:20 | Paper ID: 22 Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning Authors: Davide Giacomini (University of Illinois Chicago); Maeesha BinteHashem (UniversityofIllinoisChicago); Jeremiah Suarez (Illinois Mathematics and Science Academy); SWARUP BHUNIA (University of Florida); Amit Ranjan Trivedi (University of Illinois Chicago) |
Paper ID: 270 A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi using a 130 nm SOI CMOS Technology Author: Indrajit Das (Globalfoundries); Hari Kishore Kakara (Principal Engineer, GlobalFoundries); Vasudeva Reddy (Member of Technical Staff, GlobalFoundries); Venkata Vanukuru (GLOBALFOUNDRIES) |
Vishal Sharma, PE, iDEX DIO | Paper ID: 87 Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAs Authors: Debayan Das (Indian Institute of Science); Majid Sabbagh (Northeastern University); Rana Elnaggar (Intel Corporation); Guang Chen (Intel Corporation); Sayak Ray (Intel Corporation); Jason M. Fung (Intel Corporation) |
Paper ID: 44 Experimental Demonstration of CeO₂-Based Tunable Gated Memristor for RRAM Applications Author: Surya Shankar Dan (Professor, BITS Pilani) |
Paper ID: 150 Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile Authors: Pritam Bhattacharjee (Vellore Institute of Technology, Chennai Campus); ALAK MAJUMDER (NIT Arunachal Pradesh) |
| 12:00 PM | 12:20 PM | 00:20 | Paper ID: 45 Hardware-based Detection of Malicious Firmware Modification in Microgrids Authors: Amisha Srivastava (University of Texas at Dallas); Sneha Thakur (IEEE Member); Abraham Peedikayil Kuruvila (Samsung Electronics America); Poras T. Balsara (The University of Texas at Dallas); Kanad Basu (The University of Texas at Dallas) |
Paper ID: 284 A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity Mode Authors: Gopikrishna Vijayakumar (Indian Institute of Technology Hyderabad); Abhishek Kumar (Indian Institute of Technology Hyderabad) |
Titile: World's first - Fully Hardware based encryption Device (ABHED1) Sumit Kathavekar, Manager (Design Team), Chipspirit Technologies |
Paper ID: 163 Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment Authors: Akash Panzade (Indian Institute of Technology Kanpur); Deepak Kumar (Indian Institute of Technology Kanpur); Mahendra Rathor (IIT-BHU Varanasi); Urbi Chatterjee (Indian Institute of Technology Kanpur) |
Paper ID: 63 Artificial neural network-based solution for PSP MOSFET model card extraction Authors: Alba Ordonez (STMicroelectronics); fabien gilibert (ST Microelectronics); Francois Paolini (ST Microelectronics); Pascal Urard (ST Microelectronics); Roberto Guizzeti (ST Microelectronics); Lioua Labrak (INL Lyon); John Samuel (INL Lyon) |
Paper ID: 174 OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application Authors: Dantu Nandini Devi (International Institute of Information Technology Bangalore); Gandi Ajay Kumar (International Institute of Information Technology Bangalore); Bindu G Gowda (International Institute of Information Technology Bangalore); Madhav Rao (International Institute of Information Technology-Bangalore) |
| 12:20 PM | 12:40 PM | 00:20 | Paper ID: 91 Multiplierless In-filter Computing for tiny ML Platforms Authors: Abhishek Nair (IISc); Pallab Kumar Nath (Pandit Deendayal Energy University); Shantanu Chakrabartty (Washington University in St. Louis); Chetan Thakur (Indian Institute of Science, Bangalore) |
Paper ID: 395 A Low Power and Low Noise, Self-Body Biased Low Noise Amplifier. Authors: Jyoti Priya (IITR); Darshak Bhatt (Indian Institute of Technology Roorkee) |
Sukanta Mitra, President, ANTS Global Systems | Paper ID: 196 Enhancing Hardware Trojan Security through Reference-Free Clustering using Representatives Authors: Ashutosh Ghimire (Wright State University); Fathi Amsaad (Wright State University); Mohammed Alkurdi (Wright State University) |
Paper ID: 182 Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and Optimization of Back Gate Parameters Authors: Monika Kumari (IIT(ISM), Dhanbad); Manodipan Sahoo (IIT(ISM),Dhanbad) |
Paper ID: 224 A 0.8 V, 2.47 µW, SEU Tolerant Tri-State Inverter based SRAM Cell for SoC Applications Author: Srujana Pillay (National Institute of Technology, Goa) |
| 12:40 PM | 1:00 PM | 00:20 | Paper ID: 142 Low-Complexity Classification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator Authors: Md Najrul Islam (Indian Institute of Technology Mandi); Rahul Shrestha (Indian Institute of Technology Mandi); Shubhajit Roy Chowdhury (IIT Mandi) |
Paper ID: 396 Closed Form Expression of Input Matching of a Wideband Single-Ended to Differential LNA Authors: Sanchari Das (Department of Electrical Engineering, University at Buffalo); Bibhu Datta Sahoo (Department of Electrical Engineering, University at Buffalo) |
Paper ID: 201 Stealthy SWAPs: Adversarial SWAP Injection in Multi-Tenant Quantum Computing. Authors: Suryansh Upadhyay (Penn State University); Swaroop Ghosh (Pennsylvania State University) |
Paper ID: 341 Understanding 2-Propanol Sensing Mechanism of Pd Modified Graphene Based Gas Sensor Devices using DFT Study Authors: Indranil Maity (Assistant Professor, Department of ECE, Institute of Engineering and Management (IEM), Kolkata); Shivam Das (Institute of Engineering and Management (IEM-K), Kolkata); Rishav Dutta (Institute of Engineering and Management (IEM-K), Kolkata); Indrajit Maity (Institute of Radio Physics and Electronics (IRPE) University of Calcutta (CU)); Malay Ganguly (Institute of Engineering and Management (IEM-K), Kolkata) |
Paper ID: 234 Design and Analysis of an Area and Power Efficient Programmable Delay Cell Authors: Kuntal Chakraborty (NIT Arunachal Pradesh); Jai Gopal Pandey (CEERI Pilani); Abir J Mondal (NIT Arunachal Pradesh) |
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| 1:00 PM | 2:00 PM | 01:00 | Lunch | |||||
| 2:00 PM | 2:45 PM | 00:45 | Panel Discussion: Advancing to the Next Frontier in AI/ML Driven EDA Moderator: Sumit Goswami, Sr. Director of Engineering, Qualcomm Member | Sudeep Mondal, Director R&D, Synopsys Member | Dhiraj Goswami, Corporate Vice President R&D, Cadence Member | Ruchir Dixit, Country Manager, Siemens EDA Member | Himanshu Rawal, Sales Manager Semicon India business, Ansys Member | Dipanjan Gope, CEO, Simyog Technology |
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| 2:45 PM | 3:10 PM | 00:25 | Keynote: Title: AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency Prof. Yiran Chen, Duke University, USA |
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| 3:10 PM | 3:55 PM | 00:45 | Panel Discussion: ESDM Opportunities in India Moderator: Mr. Srinivasa Kakumanu, MosChip Member| Raghu Panicker, CEO, Kaynes Technologies Member| Prosit Mukherjee, Sr. Director Engg & Head, Noida Design Center Member| Taher Madraswala, Strategic Client Partner-Semiconductor, Quest Global Member| Prof. Debesh Das, Jadavpur University Member| Nishit Gupta, Scientist E, MeitY and Director (Technology), India Semiconductor Mission |
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| 3:55 PM | 4:25 PM | 00:30 | Tea Break | |||||
| Track31 - Technical Track AI/ ML |
Track32 - Technical Track AMS |
Track33 - | Track34-Technical Track Hardware Security |
Track35 - Technical Track Advanced Process/Material, Device Design and Modelling |
Track36 - Low-power Digital Systems |
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| Session Chair: Prof. Jimson Mathew, IIT Patna | Session Chair: Prof. Bibhoo Dutta Sahoo, Univ Buffalo | Session Chair: | Session Chair: Prof. Rajat Subhra Chakraborty, IIT KGP | Session Chair: Prof. Anirban Bhattacharyya, CU | Session Chair: Prof. Urbi Chatterjee, IIT Kanpur | |||
| 4:25 PM | 4:45 PM | 00:20 | Paper ID: 214 Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks Authors: Zeeshan Anwar (Indian Institute of Technology Guwahati); Imlijungla Longchar (Indian Institute of Technology Guwahati); Hemangee Kapoor (Indian Institute of Technology Guwahati) |
Paper ID: 389 Generation of Asymmetric Triangular Pulse by A Dispersion and Non-linearity Engineered Silicon Core Optical Fiber Authors: Atrayee Mishra (Research scholar); Binoy Ghosh (Indian Institute of Engineering Science and Technology, Shibpur); Dipankar Ghosh (Assistant Professor, Department of Basic Science ,MCKV Institute of Engineering, Liluah, Howrah); Mousumi Basu (Professor, IIEST) |
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Paper ID: 272 SRIL: Securing Registers from Information Leakage at Register Transfer Level Authors: Priyanka Panigrahi (Indian Institute of Technology Guwahati, India); Vignesh Ravichandra Rao (Indian Institute of Technology Guwahati, India); Thockchom Birjit Singha (Indian Institute of Technology Guwahati, India); Chandan Karfa (Indian Institute of Technology Guwahati) |
Paper ID: 374 Design of MoS2 based Inverter Circuits considering Interface Trap effect Authors: Sarath S (National Institute of Technology Calicut); Darshni Manekar (National Institute of Technology Calicut); Rajendra Prasad Shukla (University of Twente); Chandan Yadav (National Institute of Technology Calicut) |
Paper ID: 246 EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture Authors: Vinay Rayapati (international institute of information technology, bangalore); Sanampudi Gopala Krishna Reddy (international institute of information technology, bangalore); Ajay Kumar Gandi (international institute of information technology, bangalore); Gogireddy Ravi Kiran Reddy (international institute of information technology, bangalore); Madhav Rao (International Institute of Information Technology-Bangalore) |
| 4:45 PM | 5:05 PM | 00:20 | Paper ID: 379 Low Complexity High Speed Deep Neural Network Augmented Wireless Channel Estimation Authors: Syed Asrar ul haq (Indraprastha Institute of Information Technology Delhi); Varun Singh (Indraprastha Institute of Information Technology Delhi); Bhanu Teja Tanaji (Indraprastha Institute of Information Technology Delhi); Sumit Darak (IIIT-Delhi) |
Paper ID: 141 An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load Authors: Sowmyashree Srinivas (IIT Mandi); Hitesh Shrimali (Indian Institute of Technology Mandi) |
Paper ID: 311 ROBUST: RTL Obfuscation Using Bi-functional Polymorphic Operators Authors: Haimanti Chakraborty (University of Cincinnati); Ranga Vemuri (University of Cincinnati) |
Paper ID: 409 Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective Authors: Vivek Kumar (NIT Uttarakhand & IIT Roorkee); Nischal Anand (NIT Uttarakhand); Rohit Rai (NIT Uttarakhand); Sneha Chauhan (NIT Uttarakhand); Jyoti Patel (Indian Institute of technology Roorkee) |
Paper ID: 289 FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation Authors: Ayan Palchaudhuri (Indian Institute of Technology Bhubaneswar); Anindya Sundar Dhar (Indian Institute of Technology Kharagpur) |
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| 5:05 PM | 5:25 PM | 00:20 | Paper ID: 424 FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing Authors: Yathin Attuluri (International Institute of Information Technology Bangalore); Ruchit Chudasama (IIT Gandhinagar); Kailash Prasad (Indian Institute of Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar) |
Paper ID: 325 Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme Authors: Rohan Sinha (Texas Instruments India Pvt. Ltd.); Devraj M. Rajagopal (Texas Instruments India Pvt. Ltd); Aditya Madhavan (Texas Instruments India Pvt. Ltd) |
Paper ID: 364 Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers Authors: Vishesh Mishra (Indian Institute of Technology Kanpur); Sparsh Mittal (IIT Roorkee); Nirbhay Mishra (Chandigarh University); Rekha Singhal (TCS Research) |
Paper ID: 50 Experimental Demonstration of SnO₂ Nanofiber-Based Memristors and Their Data-Driven Modeling for Electronic Circuit Applications Author: Surya Shankar Dan (Professor, BITS Pilani) |
Paper ID: 410 A High Performance and Low Power Subthreshold Voltage Level Shifter Design Authors: Ananya Kapoor (Delhi Technological University); Ayush Thapar (Delhi Technological University); Chaitanya Shanker Jha (Delhi Technological University); Dr. Inder Kumar Choudhary (Delhi Technological University) |
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| 5:25 PM | 5:45 PM | 00:20 | Paper ID: 429 COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators Authors: Vrajesh Patel (Indian Institute of Technology Gandhinagar); Neel Shah (Indian Institute of Technology Gandhinagar); Aravind Krishna (Indian Institute of Technology Gandhinagar); Tom Glint (Indian Institute of Technology Gandhinagar); Abdul Ronak (Indian Institute of Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar) |
Paper ID: 64 Wear Leveling-Aware Active Battery Cell Balancing Authors: Enrico Fraccaroli (University of North Carolina at Chapel Hill); Seongik Jang (Hyundai Motor Company); Logan Stach (UNC Chapel Hill); Hoeseok Yang (Santa Clara University); Sangyoung Park (Technical University of Berlin); Samarjit Chakraborty (UNC Chapel Hill) |
Paper ID: 433 Quantifying the Efficacy of Logic Locking Methods Authors: Deepali Garg (Carnegie Mellon University); Joseph Sweeney (Amazon); Larry Pileggi (Carnegie Mellon University) |
Paper ID: 157 Power Integrity Analysis for Interoperability of BoW Chiplet Interfaces Authors: Ishan Mishra (Indian Institute of Technology Bombay); Jayaprakash Balachandran (d-Matrix); Wen-Sin Liew (d-Matrix Inc.); Elad Alon (Blue Cheetah Analog Design Inc.); Srinivas Venkataraman (Meta Platforms Inc.); Shalabh Gupta (IIT Bombay) |
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| 5:45 PM | 6:30 PM | 00:45 | Wrap Up Session | |||||
