| 5 |
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application |
Shriharsh Prasad Behera (National Institute of Technology Raipur); Mahesh Vaidya (Indian Institute of Science); Alok Naugarhiya (National Institute of Technology Raipur) |
| 236 |
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs |
Om Maheshwari (Indian Institute of Technology Gandhinagar); Dev Vyas (Pandit Deendayal Energy University); Nihar Mohapatra (Associate Professor) |
| 261 |
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis |
SHIVENDRA SINGH (IIIT Delhi); EKTA TIWARI (IIIT Delhi); ABHINAV GUPTA (IIIT Delhi); SNEH SAURABH (IIIT Delhi) |
| 98 |
Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA |
Nidhee Bhuwal (Dr Shyama Prasad Mukherjee International Institute of Information Technology, Naya Raipur); Manoj Kumar Majumder (Dr Shyama Prasad Mukherjee International Institute of Information Technology, Naya Raipur); Deepika Gupta (Dr Shyama Prasad Mukherjee International Institute of Information Technology, Naya Raipu) |
| 118 |
Design of 3 bit/cell NAND Memory Array based on Ferroelectric Field Effect Transistor |
Albert Daimari (Tezpur University); Ankit Chakusaru Deori (Tezpur University); Arnab Ratna Pawe (Tezpur University); RATUL KUMAR BARUAH (Tezpur University) |
| 212 |
Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel |
Minal Bisen (Indian Institute of Technology Bhilai); Kapil Jainwal (Indian Institute of Technology Hyderabad); Nitin Khanna (Indian Institute of Technology Bhilai) |
| 290 |
Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits |
Zainubia Zainubia (GCET Jammu); Bipul Kumar Singh (IIT Jammu); Manish Pundir (IIT Jammu); Subhash Chander Dubey (IIT Jammu); Ambika Prasad Shah (IIT Jammu) |
| 317 |
A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and <-255-dB FOMjitter |
ANSHUL VERMA (Indian Institute of Technology Roorkee); BISHNU PRASAD DAS (IIT Roorkee) |
| 428 |
An Integrated Multipurpose Low-Power Electrochemical Readout Interface with On-Chip Input Waveform Generator |
Sayan Sarkar (HKUST) |
| 93 |
Optimizing Medical Image Analysis: Leveraging Efficient Hardware and AI Algorithms |
Subhadeep Dolai (Liverpool John Moores University); Ekata Mitra (Portland State University); Hafizur Rahaman (Indian Institute of Engineering Science and Technology,Shibpur) |
| 95 |
SpiCS-Net : Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks |
Manu Rathore (University of Tennessee); Garrett S. Rose (University of Tennessee) |
| 152 |
Nano-watt Hyperdimensional Compute-in-Memory and Storage using Linear Floating-gate Injectors |
Darshit Mehta (Ginko Bioworks Inc.); Shantanu Chakrabartty (Washington University in St. Louis) |
| 253 |
Reconfigurable Processing-in-Memory Architecture for Data Intensive Applications |
Sathwika Bavikadi (George Mason University); Purab Ranjan Sutradhar (Rochester Institute of Technology); Amlan Ganguly (Rochester Institute of Technology); Sai Manoj Pudukotai Dinakarrao (George Mason University) |
| 339 |
HARVEST: Towards Efficient Sparse DNN Accelerators using Programmable Thresholds |
Soumendu Ghosh (Intel Corporation); Shamik Kundu (University of Texas at Dallas); ARNAB RAHA (Intel Corporation); Deepak A. Mathaikutty (Intel Corporation); Vijay Raghunathan (Purdue University) |
| 423 |
FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC |
Saketh Gajawada (InternationalInstituteofInformationTechnologyBangalore); Aryan Gupta (IIT Gandhinagar); Kailash Prasad (Indian Institute of Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar) |
| 147 |
Early RTL Exploration and Debug of Static DFT Verification in Mobile SoC and Edge AI Applications |
Vinod Viswanath (Real Intent, Inc.); Kanad Chakraborty (Real Intent) |
| 42 |
DRL-based Multi-Stream Scheduling of Inference Pipelines on Edge Devices |
Danny Pereira (IIT Kharagpur); Sumana Ghosh (Indian Statistical Institute); Soumyajit Dey (IIT Kharagpur) |
| 159 |
A Pulse Oximeter And a Controller Designed For Automatic Regulation of Oxygen Concentrators |
DIBYA CHOWDHURY (Indian Institute of Technology Ropar); Shivdeep Shivdeep (Indian Institute of Technology Ropar); Devarshi Mrinal Das (Indian Institute of Technology Ropar) |
| 298 |
An Efficient Neural Network Controller for Autonomous Lane-Keeping Assist System |
Debanjan Mallik (Jadavpur University); Sumana Ghosh (Indian Statistical Institute) |
| 151 |
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures |
Fatemeh Shirinzadeh (University of Bremen); Arighna Deb (School of Electronics Engineering, KIIT University); Saeideh Shirinzadeh (German Research Center for Artificial Intelligence (DFKI)); Abhoy Kole (German Research Center for Artificial Intelligence (DFKI)); Kamalika Datta (University of Bremen); Rolf Drechsler (University of Bremen/DFKI) |
| 215 |
Accelerating Fluid Loading in Sample Preparation with Fully Programmable Valve Arrays |
Mohit Kumar (Havells); Abhik K. Khan (IIT Guwahati); Sudip Roy (IIT Roorkee); Krishnendu Chakrabarty (Arizona State University); Sukanta Bhattacharjee (Iitg) |
| 255 |
Analysis of the Effects of Crosstalk Errors on Various Quantum Circuits |
Soumen Bajpayee (Indian Institute of Information Technology Kalyani); Imon Mukherjee (Indian Institute of Information Technology Kalyani) |
| 427 |
Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications |
Monika Pokharia (Indian Institute of Technology, Gandhinagar); Kailash Prasad (Indian Institute of Technology Gandhinagar); Ravi Hegde (Indian Institute of Technology, Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar) |
| 13 |
Design for Trust utilizing Rareness Reduction |
Aruna Jayasena (University of Florida); Prabhat Mishra (University of Florida) |
| 193 |
KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA |
Suraj Mandal (IIT Kanpur); Debapriya Basu Roy (Indian Institute of Technology Kanpur) |
| 195 |
Pattern Based Synthetic Benchmark Generation for Hardware Security Applications |
Juneeth kumar Meka (University of Cincinnati); Satya AmarKant Marupureddy (University of Cincinnati); Ranga Vemuri (University of Cincinnati) |
| 203 |
Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive |
Sivaraman R (Research Scientist); Muralidaran D (Faculty); Muthaiah R (Professor); Shankar Sriram V S (Professor) |
| 232 |
A High Throughput ASCON Architecture for Secure Edge IoT Devices |
Ayyappa Koppuravuri (International Institute of Information Technology Bangalore); Haribabu Pasupuleti (International Institute of Information Technology Bangalore); Sasirekha GVK (International Institute of Information Technology Bangalore); Jyotsna Bapat (International Institute of Information Technology Bangalore) |
| 354 |
Enhancing Output Corruption Through GSHE Switch Based Logic Encryption |
Nikhil Saxena (University of Cincinnati); Ranga Vemuri (University of Cincinnati) |
| 414 |
Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. |
Praveen Karmakar (IIT Guwahati); Marpina Bharani (IIT Guwahati); Chandan Karfa (Indian Institute of Technology Guwahati) |
| 416 |
Trojan Localization using Information Flow Tracking Properties in SoC Designs |
Suriya Srinivasan (University of Cincinnati); Ranga Vemuri (University of Cincinnati) |
| 417 |
Processing-in-Memory Architecture with Precision-Scaling for Malware Detection |
Sreenitha Kasarapu (George Mason University); Sathwika Bavikadi (Geroge Mason University); Sai Manoj Pudukotai Dinakarrao (George Mason University) |
| 422 |
SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space |
Kailash Prasad (Indian Institute of Technology Gandhinagar); Neel Shah (Indian Institute of Technology Gandhinagar); Jinay Dagli (Indian Institute of Technology Gandhinagar); Joycee Mekie (Indian Institute of Technology Gandhinagar) |
| 247 |
Multi Port Register File Implementation Using SDP Approach For Optimized Area and Power |
vijay kumar vala (mediatek); priyanka gupta (mediatek) |
| 376 |
Broadband spectrum generation in Silicon nanocrystal-based dual-slot waveguide |
SOMEN ADHIKARY (Senior Research Scholar); Ritesh Das (Junior Research Scholar); Mousumi Basu (Professor) |
| 7 |
A Novel Approach to Control a DC-DC Converter Using its Empirical Physical Model |
Sushmita Ghosh (PhD Scholar, Indian Institute of Technology Delhi); Bidyut K. Bhattacharyya (Professor, School of Electrical and Computer Engineering, Georgia Institute of Technology) |
| 92 |
A novel controlled shutdown scheme for DC-DC converters enabling energy recycling |
Anup Deka (Intel); Shobhit Tyagi (Intel) |
| 59 |
Evolvable Hardware for Fault Mitigation in Control Circuits |
Deepanjali S (Indian Institute of Information technology Design and Manufacturing, Kancheepuram); Noor Mahammad Sk (Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram); Beautlin S (St.Joseph's Institute of Technolology, Chennai) |
| 69 |
On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules |
SABYASACHEE BANERJEE (Asst. Prof.); Subhashis Majumder (Prof.); Bhargab B. Bhattacharya (Prof.) |
| 202 |
Structural Testing: Vmin Silicon Issues and Solutions |
Prashant Sonone (Mr); Pradeep R (Mr) |
| 432 |
Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs |
Tanusree Kaibartta (Dr.); Hitarth Arora (IITISM); Debesh Kumar Das (Jadavpur University) |
