Call for papers

Hardware for AI and ML: Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence, AI accelerator design, AI boosted circuits and systems for Brain Machine Interface, Intelligent storage, Memory Centric Accelerator Design, Low power autonomous systems, Trusted Architectures for AI

Analog & Mixed Signal circuits: Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces.

Photonic Integrated Circuits: Silicon and III-V Photonic Integrated Circuits, Waveguides/interconnects, On-chip lasers, Optical Multiplexers/Demultiplexers, Photo detectors and sensors, Quantum photonics, RF Photonics, Mid-IR/THz Photonics, Heterogeneous integration, Packaging of Photonic devices, Quantum photonics, RF Photonics, Mid-IR and THz Photonics.

RF Circuits and Wireless systems:  RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging. Reliability aspects in RFICs.

Wireline and Optical Communication Circuits and Systems: Receivers/transmitters/transceivers for wireline systems, exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation and distribution circuits including PLLs, line drivers, and hybrids).

Sensors interfacing circuits and systems: Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits and systems for IoT.

Neuromorphic Circuits and Systems:  Device, circuit, architecture design, analysis and optimization for neuromorphic computing systems, Complexity and scalability of neuromorphic computing, Emerging technologies for brain-inspired nano-computing and communication, Applications of neuromorphic computing in embedded and IoT devices, unmanned vehicles and drones, and cyber-physical systems.

Embedded Systems, Internet of Things (IoT), and Cyber-Physical System (CPS)Design: ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems, Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip, Embedded for automotive and Electric Vehicles, Artificial Intelligence of Things (AIoT), Edge Intelligence, Reconfigurable computing for IoT and CPS, Design automation for IoT/CPS.

Low-power Digital Systems: Next generation digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Energy-efficient storage systems, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.

Advances in CAD for VLSI: Logic and behavioral synthesis, logic mapping, simulation and formal verification, physical design techniques, post route optimizations, simulation Tools for Design Verification, Static Timing and Timing Exceptions, Mixed Signal Simulations in sub 10 nm nodes, Application of Machine Learning in CAD for VLSI, CAD for Secured Chips

Latest trends in device design and modelling: Deep nanoscale CMOS devices, device modeling and simulation, multi-domain simulation, device/circuit-level reliability and variability, Devices for beyond CMOS, compact modeling and novel TCAD solutions.

Beyond 2D in Packaging and interconnects: Methodologies and tools forWafer-level packaging, embedded chip packaging, 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation, component, system and product level thermal management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects.