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40th Edition Jan 2–6, 2027
Sheraton Grand, Bengaluru

Call for Papers

40th International Conference on VLSI Design & 26th International Conference on Embedded Systems, Bengaluru, India

Call for Papers

The Technical Program Committee cordially invites researchers, academicians, industry professionals, innovators, entrepreneurs, and students from around the world to submit their original research contributions to the 40th International Conference on VLSI Design and the 26th International Conference on Embedded Systems, to be held in Bengaluru, India. As India’s premier conference on semiconductor design, electronic systems, and embedded technologies, this landmark edition provides a distinguished platform for experts from academia, industry, research laboratories, startups, and government organizations to present cutting-edge innovations, exchange ideas, foster collaborations, and shape the future of VLSI, semiconductor technologies & manufacturing. The high-level topics/track are listed below based on this years theme for the conference.

1: VLSI CHIP DESIGN

  1. Electronic Design Automation (EDA)
    1. Logic and behavioral synthesis
    2. Physical design techniques & Post-route optimizations
    3. Static Timing Analysis and timing exceptions; 
    4. EDA for sub-10nm nodes
    5. Design for Debug (DFD) tools;
    6. Application of AI/ML in CAD for VLSI
    7. Optimization of Placement and Routing, 
    8. AI for placement and Routing, 
    9. CAD for printed circuit boards (PCBs)
    10. CAD for secure chips. 
    11. EDA and physical design tools, processes, methodologies, and flows,
    12. Design tools for analysis/ tolerance of variation, aging, and soft-errors,
    13. Design and maintenance of hard and soft IP blocks, 
    14. EDA for non-traditional problems such as smart power grid and solar energy, 
    15. CAD for bio-inspired and neuromorphic systems, 
    16. EDA tools, methodologies and applications for MEMS, Photonics devices, circuit and system design Large language models (LLMs) for CAD
  2. Analog and Mixed Signal & RF circuits
    1. Amplifiers, comparators, oscillators and filters
    2. Nonlinear analog circuits
    3. Digitally-assisted analog circuits; 
    4. Analog design at lower technology nodes,
    5. Analog Circuits for Various Applications, Data Converters, High Speed Interfaces. RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, 
    6. Reliability aspects in RFICs
  3. Logic, Circuit & Low Power Design 
    1. Next-generation digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor
    2. Near- and sub-threshold systems
    3. Energy-efficient algorithms and applications
    4. Energy-efficient storage systems
    5. Digital circuits for intra-chip communication, clock distribution, low-power and robust design
    6. Digital regulators and digital sensors,
    7. Advances in memory architectures for power reduction,
    8. Design for low-power FPGA, GPU, NPU and TPU
    9. Low power design and optimization at circuit, device and system level
    10. Circuit design techniques for digital, memory, analog, and mixed-signal systems
    11. Circuit design techniques for high performance and low power
    12. Circuit design techniques for robustness under process variability, electromigration, and radiation
  4. Reconfigurable Computing & Processor Design
    1. Autonomous/adaptable/reconfigurable systems and architectures
    2. FPGA Accelerator Design, Placement & Routing of FPGA layout
    3. Hardware support for processor virtualization
    4. HW/SW prototyping and emulation on FPGAs, Application driven heterogeneous computing platforms
    5. High-performance, energy-efficient multi-core and many-core (heterogeneous) processor architectures
    6. RISC-V based systems
    7. Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip
    8. Techniques for low-power, secure, and reliable processor architectures
    9. Coarse grained reconfigurable architectures (CGRA)
    10. High-level synthesis on reconfigurable architectures
  5. Hardware and System Security
    1. Secure and trustworthy hardware
    2. Side-channel attack (SCA), fault attacks, and mitigation
    3. Hardware trojan attacks and mitigation
    4. Automotive security
    5. Physically unclonable functions (PUF)
    6. Hardware design for fully homomorphic encryptions, security of Trusted architectures and polynomial multipliers
    7. Micro-architectural security attacks and countermeasures including but not limited to side-channel attacks, reverse engineering, tampering, and trojans
    8. Hardware-based security primitives including PUFs, TRNGs and ciphers
    9. Security, privacy, trust protocols, and trusted information flow
    10. Ensuring trust using untrusted tools, IP, models and manufacturing
    11. Secure hardware architectures and memory systems
    12. Post-quantum security primitives/cryptography
    13. Reconfigurable fabric security
    14. Hardware security for AI models
    15. Security challenges and opportunities of emerging nanoscale devices, IoT and cyber-physical system security
  6. Test, Verification and Reliability 
    1. Simulation, formal verification, validation at different abstraction levels
    2. All areas of DFT, ATE and BIST for digital designs, analog/mixed-signal IC’s, SoC’s, and memories
    3. Post-silicon validation and debug; Delay test and speed-binning
    4. Memory test, reliability and fault tolerance
    5. 2.5D/3D IC testing 
    6. Analog and mixed-signal testing 
    7. Hardware and software formal-assertion and simulation-based design verification techniques
    8. Test synthesis and synthesis for testability, fault diagnosis, IDDQ test, novel test methods, fault models and ATPG, and DPPM prediction
    9. SoC/IP testing strategies
    10. Hardware/software co-verification, 
    11. Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs), 
    12. Formal and semi-formal verification and validation techniques, Safety and security in verification and validation
    13. New methods and tools supporting functional safety and security
    14. Self-checking testbenches in analog verification
    15. Large language models (LLMs) for design & verification 
    16. Reliability, soft-errors and aging prediction and yield defects detection
    17. Power and Signal integrity
    18. Static/dynamic defect- and fault-recoverability 
    19. High-frequency electromagnetic and circuit simulations
  7. Hardware for Machine Learning (ML) & Artificial Intelligence (AI) 
    1. Architecture and circuit innovations for ML/AI
    2. Accelerator design for AI/ML applications, LLMs, federated Learning and multi-agent systems
    3. AI boosted circuits and systems for Brain Machine Interface
    4. Intelligent storage and memory centric accelerator design
    5. Trusted architectures for AI and adversarial machine learning
    6. Approximate Computing for AI acceleration
    7. Hardware/Software Co-design, reconfigurable architectures for AI/ML

2: Semiconductor Technologies & Devices 

  1. New device and process technology
  2. Modelling and simulation of semiconductor processes and devices (TCAD)
  3. Deep nanoscale CMOS device modeling and simulation
  4. Multi-domain simulation, device/circuit-level reliability and variability
  5. Devices for beyond CMOS, compact modeling and novel TCAD solutions
  6. RF and microwave semiconductor devices
  7. Optoelectronic devices
  8. High-frequency and high-speed devices
  9. Photonics interconnect
  10. 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation
  11. System and product level thermal management and characterization
  12. Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects
  13. Innovative packaging technologies including 3D IC, 2.5D or interposer and multi-chip module and their impact on system design
  14. Design techniques, methodologies and flows for vertically integrated circuits/chips
  15. Modeling and mitigation of device interactions for 3D ICs
  16. Design of die-to-die interfaces in 3D/2.5D ICs
  17. Design-for-testability and system-level design issues in 3D/2.5D, Die-package co-design
  1. Power and Energy Management
  1. Power management and control circuits and regulators
  2. Power converter ICs, energy harvesting circuits and systems
  3. Wide-bandgap topologies and gate-drivers
  4. Power and signal isolators
  5. Power management for automotive systems, battery management circuits and systems

3: Semiconductor & Electronics Manufacturing 

  1. Printed Circuit Board (PCB) manufacturing
  2. Surface Mount Technology (SMT) and assembly processes
  3. Electronic manufacturing services (EMS)
  4. Methodologies and tools for wafer-level packaging and embedded chip packaging
  5. MEMS fabrication technologies
  6. Sensor manufacturing and integration
  7. Manufacturing process optimization and yield improvement
  8. Semiconductor wafer fabrication technologies
  9. Advanced process nodes and manufacturing challenges
  10. Lithography technologies (DUV, EUV, Nanoimprint)
  11. Etch, deposition, CMP, and process integration
  12. Compound semiconductor manufacturing (GaN, SiC, GaAs, InP)
  13. Semiconductor equipment and process control technologies
  14. OSAT & Supply Chain Ecosystem
  15. Smart factories and Industry 4.0 for electronics manufacturing
  16. AI, Automation & Digital Manufacturing

4: Emerging Technologies

  1. Cryogenics electronics for processors & sensors. Control & Readout quantum systems, 
  2. Quantum Information processing systems
  3. Quantum logic circuits and Quantum algorithms
  4. Spin-based computing, reversible computing, approximate and stochastic computing
  5. Quantum machine learning
  6. EDA for quantum chip design
  7. Neuromorphic computing
  8. In-memory/near-memory computing
  9. Post-CMOS Technologies
  10. Chiplets based heterogeneous system design
  11. Emerging memory technologies
  12. Bio-inspired or Genomics on chip

5: Intelligent Systems

  1. Embedded  Systems, IoT & Cyber Physical Systems 
    1. Many and multi-core SoC architecture
    2. Embedded systems language (ESL) and system-level design methodology 
    3. Networks-on-chip
    4. Fault-tolerant architectures and  Real-time embedded systems
    5. Embedded software including operating systems, firmware, middleware, communication, virtualization, encryption, compression, security and reliability
    6. Compiler and tool chain
    7. Embedded systems for automotive and Electric Vehicles (EVs)
    8. In-Vehicle Networks and Communication Systems
    9. Automotive sensors and sensor fusion
    10. 5G/6G for Connected Vehicles
    11. Vehicle-to-Vehicle (V2V) communication
    12. Vehicle-to-Infrastructure (V2I) communication
    13. Software-Defined Vehicles (SDV)
    14. Edge intelligence and  Artificial Intelligence of Things (AIoT)
    15. MedTech devices and systems, sensor interfacing, biomedical circuits and healthcare systems
    16. Wearable electronics, flexible electronics, ultra-low power circuit techniques, circuits, 
    17. Smart Agritech IoT/CPS systems
  2. Smart Cities, Transportation & Industrial Automation 
    1. Intelligent Transportation Systems
    2. Smart Energy Management
    3. Intelligent Water and Waste Management
    4. Smart Buildings and Infrastructure
    5. Public Safety and Security Systems
    6. Sustainable Intelligent Cities
    7. Industrial IoT, digital twin for manufacturing, Industry 4.0

Key Dates

  • Submission Deadline: 7th Aug 11:59 PM Pacific Standard Time (Monday)
  • Acceptance Notification: September 28th, 2026 (Monday)
  • Author Registration: November 9th, 2026 (Monday)
  • Camera-Ready Format Submission: November 9th, 2026 (Monday)

Submission Format

  • Full paper: Maximum 6 pages
  • Abstract: Up to 300 words
  • IEEE two-column conference format
  • Double-blind review (author names omitted from manuscript)
  • PDF electronic submission via SoftConf Link provided below.