User Design Track

Important Dates

✓ Final date of submission:
Closed
✓ Notification of acceptance:
Closed
✓ Final Presentation date:
Jan 10, 2023 📅

✓ Final date of submission: Closed
✓ Notification of acceptance: Closed
✓ Final Presentation date: Jan 10, 2023 📅

Topics

Artificial Intelligence, Machine Learning and their Applications

AI Accelerators, Edge Computing, Approximate Computing, Autonomous Intelligence (ADAS), AI ethics

Security and Safety

Functional Safety, Privacy, Cryptography, PUFs, TRNGs, Hardware Trojans, Trusted Computing, Network Security, Side-Channel and Fault Analysis and Countermeasures

Analog and Mixed Signal Design

Analog Circuits for Various Applications, Data Converters, High Speed Interfaces, Power Management Circuits, Energy Harvesting Circuits & Systems, Circuits & Systems for AI-oriented Applications

Sensors Circuits and Systems

Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Autocalibration Techniques, Wearable Electronics, Autonomous Sensors Systems

Digital Integrated Circuits and Systems

Digital Circuits for Communication, Arithmetic Circuits, System-on-Chip Design, Network-on-Chip Design, Low-power Logic Design

Power Electronics

High Power Circuits, Power Convertors, Power Optimization Techniques, Power Delivery Networks, Power Switches, High Voltage Circuits and Systems, Power Management for High Voltage Applications, Power Amplifiers

Low power Digital Architectures

Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.

RF Circuits and Systems

Transceiver Architectures, Short-Range Communication, IoT/IoE, WPAN, Ultra-Low Power Wireless Designs, Effective Spectrum Utilization, RF Power Amplifiers, RF Energy Harvesting

Emerging Technologies and Devices

Quantum Computing, Neuromorphic Computing, Synaptic Devices, CMOS Technology and Devices, New Age Nano-Electronics, MEMS Devices, GaN and SiC Devices

Test and Reliability

EMIR, Interconnect, Power Integrity-Signal Integrity (PISI), EMI/EMC Compatibility, Built-in Self-Test, Design for Test, Self-X (Awareness, Repair, Test), On-line Test, Fault Tolerance

Embedded System Design

IoT Systems, Cyber-Physical Systems, Hardware/Software Co-design, Embedded Software, Embedded Operating Systems

Architectures

Chip Architecture, Computer Architecture, High Performance Computing, Configurable Computing, (Embedded) FPGA, Memory Subsystems, In Memory Computing Systems

Electronic Design Automation

Verification, Synthesis, Physical Design, Silicon Engineering, Just-in-time Synthesis, AI enabled algorithms, Formal Verification, Optimization

Packaging and Interconnects

On-chip interconnects, 3D packaging, Wafer-level packaging, Interconnect Technologies

Please Note

  • All presentation submissions to User Design Track should be made electronically via the below submit button before the due date.
  • Use provided presentation template only. You can download presentation template below.
  • Maximum 8 slides can be used (including 1 title, 6 content and 1 thank you slide). All figures, references should be incorporated in this limit. The submission should be done in pdf format only.
  • Presentation should clearly state the problem statement/novel ideas, proposed solution (results, and applications) of the contribution, silicon results if relevant/available.
  • Use speaker notes to provide more details to the reviewer wherever necessary.
  • Presentation exceeding the page limit or identifying the authors/organization will be rejected without review.
  • Submissions will undergo a double-blind review.
  • For selected presentation, authors need to submit recorded video of the presentation. Further details will be shared with the selected authors after acceptance notification.

For questions contact: [email protected]

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