39 th International Conference
On VLSI Design

VLSID VLSID
3rd - 7th January 2026 | JW Marriott | Pune, India

25 th International Conference
On Embedded Systems

Global Synergy in Silicon: VLSI and Embedded AI for Sustainable Computing and Next-Gen Electrified Mobility

User Design Track VLSID 2026

Real-World Innovations. Real-World Impact.

Call for User Design Track Presentations

Important Dates

Final date of submission: 20th September, 2025

Notification for Acceptance: 30th November, 2025

Final Presentation Submission: 7th December, 2025

The convergence of Very Large Scale Integration (VLSI) technology and embedded artificial intelligence (AI) is revolutionizing the landscape of next-generation electrified mobility. As the world accelerates its transition toward sustainable and energy-efficient transportation systems, there is a rising demand for intelligent, high-performance, and low-power electronics. When coupled with embedded AI, the VLSI systems gain the ability to learn, adapt, and optimize performance in dynamic driving environments. From battery management and predictive maintenance to autonomous navigation, the synergy between VLSI and AI holds the key to unlocking smarter, greener mobility solutions. Within the realm of VLSI and Embedded Systems, the focus has shifted toward accelerated computing, sensing, wireless connectivity, big data, secure connectivity and data conversion. To support this evolution, significant advancement has been observed in EDA/CAD automation, design and manufacturing, and Quantum Computing.

The User Design Track provides a unique platform to showcase cutting-edge work that is happening in the industry to a wider audience. The unique slides-only format for UDT allows for simplified and faster preparation for submission. The UDT committee invites high-quality submissions targeting challenges, innovations, WIP, late breaking results on the wide range of topics, including but not limited to:

Topics

  • Generative AI and Foundational Models in System Design
  • Hardware and Systems for Large Language Models (LLMs) Acceleration
  • Agentic AI Architectures
  • Hardware for Machine Learning and Artificial Intelligence
  • Embedded AI
  • Analog & Mixed Signal and, RF Circuits
  • Sensors interfacing circuits and systems
  • VLSI for Automotive Circuits and Systems
  • Test, Verification and Reliability
  • Embedded Systems, Internet of Things (IoT), and Cyber-Physical System Design
  • Electronic Design Automation
  • Low power Digital Systems
  • Advances in CAD for VLSI
  • Latest trends in device design and modeling
  • Beyond 2D in Packaging and interconnects
  • Hardware and Systems Security
  • Emerging Memory Technologies
  • Wireless Systems, 5G and beyond
  • Power & Energy Management
  • Emerging Computing & Post-CMOS Technologies
  • Quantum Computing
  • FPGA Architecture Design – Layout Design, Open FPGA
  • Neuromorphic Computing – Spiking Neural Networks, Neuron models
  • Chiplet-based heterogeneous designs

Submission Guidelines:

  • Submissions must be made electronically before the due date.
  • Submissions must be in PDF format and use the provided presentation template.
  • Submissions must be limited to a total of 10 slides (including title slide, references/acknowledgement slide). Authors' names & affiliations must NOT be included in the presentation while submitting.
  • New authors' names cannot be added after the initial submission is done.
  • Presentation should clearly state the Problem Statement/Motivation, Proposed Solution, Novelty elements, Evidence, Applications, Silicon results, and Future work.
  • Authors can use speaker notes to provide additional details to reviewers wherever required.
  • Submissions will undergo a double-blind review. Submissions exceeding the slide limit or identifying the authors/affiliation will be rejected without review.
  • At least one author from every accepted submission MUST register and present at the conference. Authors will also need to submit recorded video of the presentation.

Please submit your enquiries at: