Global Synergy in Silicon: VLSI and Embedded AI for Sustainable Computing and Next-Gen Electrified Mobility
Design Contest VLSID 2026
Challenge Your Creativity. Shape the Future.
The 39th International Conference on VLSI Design and the 25th International Conference on Embedded Systems are conducting the Design Contest to provide a platform to showcase semiconductors driving disruptive innovations in several areas such as AI/ML applications, automotive, IoT, motor control, healthcare, robotics, communications, and signal processing.
Important Dates
- Last date for Proposal submission:
14 Sep 2025 AOE/ 21 Sep 2025 AOE - Acceptance notification: 28 Sep 2025 AOE
- Kits availability to selected teams: 5 Oct 2025 AOE
- Final project submission: 30 Nov 2025 AOE
- Final project acceptance: 5 Dec 2025 AOE (5 from each category)
Platforms
Choose one of the three platforms available to implement proposed idea. Some example applications for the target platforms are also listed.
Platform 1: Lattice Semiconductor’s
Lattice Semiconductor’s CPNX VVML FPGA platform targeted for:
- AI/ML – Object Detection and Classification, Face Detection, intruder notification, Camera-based Object Sorting
- Defect detection for Industrial applications
- Predictive Maintenance using audio analytics
- IoT – Medical-Patient Monitoring System, Home Automation, Industrial
- Robotics with ROS
- Automotive- ADAS
Additional information available on the below links:
Platform 2: Microchip Technology’s
Microchip Technology’s RISC-V based PolarFire® SoC Icicle Kit targeted for:
- Battery management system
- AI/ML Object Detection and Classification
- Body Control Module (Simple warnings like door ajar, low fuel, lights on etc.).
- Automotive – ADAS
- DSP/Communications related applications, Systems, Audio Processing.
- Robotics – Motor Control, Vision etc.
Additional information:
Students can use external modules and can plug in to ICICLE Kit.
Platform 3: Designing Qubit
Designing Qubit using Qiskit Metal. Both 1 and 2 need to be submitted.
- Design a single Transmon qubit with a readout resonator Qiskit Metal Platform. Key aspects should include (1) Design & Implementation and (2) Analysis & Validation
- Formulate a project idea leveraging Qiskit Metal. Discuss its approach & application.
Additional information available on the below links:
Stages of Design Contest
Stage-1: Proposal Submission
- Submission must be in PDF format and according to these templates. Template for Platform 1 and 2. Template for Platform 3. (Use the Links available below).
- Submission must be in Times New Roman, 10pt font and limited to a total of 2 pages for platform 1, 2. Platform 3 submission must be limited to 7 pages (2 pages for proposal and 5 for Qubit design details).
- Only one platform must be chosen from the listed platforms.
- At least one author from every accepted submission MUST register and present at the conference.
- New authors’ names cannot be added after the initial submission is done.
- The committee’s decision on acceptances will be final.
- Submission must be made electronically
Stage-2 : Implementation
- After the first round of screening, teams will be shortlisted to convert their ideas into applications/solutions using the platform proposed during submission.
- Hardware kits will be shipped to the selected teams.
- Experts from the respective conference teams will mentor/guide them while implementing the design.
Stage-3: Presentation
- After the second round of screening, teams will be shortlisted to present their work at the VLSID conference.
Selection Process and Awards
- Stage 1: After proposal submission, 10 projects/teams will be selected from each category/platform (a total of 30 teams).
- Stage 2: After final project submission, 5 projects/teams from each category will be selected to present at the VLSID Conference (a total of 15 teams).
- Stage 3: After the presentations at the conference, 1 project/team per category will be selected for the best project award (a total of 3 awards). Prize money of Rs. 50k will be awarded for the winning team from each category.
Eligibility
- B.E./B.Tech/B.Sc. (2nd, 3rd, 4th year), M.Tech., M.S., M.Sc, PhD.
- A minimum of 2 and a maximum of 4 students in the team plus a faculty mentor (required) from the institute.