39 th International Conference
On VLSI Design

VLSID VLSID

25 th International Conference On Embedded Systems

3rd - 7th January 2026 | JW Marriott | Pune, Maharashtra, India.

Global Synergy in Silicon: VLSI and Embedded AI for Sustainable Computing and Next-Gen Electrified Mobility

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Explore the full schedule of keynotes, technical sessions, panels, workshops, and networking events happening throughout VLSID 2026 in Pune.

VLSID 2026 – Detailed Agenda

Agenda.pdf

Registration

Collect your badges at the registration desk.

Time: 8 AM to 9 AM

Keynote : TBD

Vivekanand Auditorium

Time: 9:00 AM to 9:30 AM

Track Chair: Hall 1 Chair
9.30 AM to 11 AM
Supercharge your RISC-V Designs with Higher Abstraction Shift-Left
Ayush Mewati & Aditya Tiwari - CircuitSutra Technologies
11 AM to 11.30 AM
Tea Break – Take a breather, sip some chai, and spark meaningful conversations.
11.30 AM to 1.00 PM
Safe and Secure RISC-V Processors for Software-Defined-Vehicles
Sourav Roy & Neha Srivastava - NXP
1.00 PM to 2.00 PM
Lunch Break – Refuel and recharge while networking with fellow innovators.
2.00 PM to 3.30 PM
Foundry Compliance and Tapeout Readiness - A Complete Framework from Design Verification to Silicon Qualification
Venkata Reddy Kolagatla & Vivian Desalphine - CDAC
3.30 PM to 4.00 PM
Tea Break – Recharge with an evening brew and spark fresh ideas for the final sessions.
4.00 PM to 5.30 PM
Physical Design and Timing Closure challenges in advance technology nodes
Vinayak Mehetre - Qualcomm