User Design Track
Important Dates
Final date of submission : Is Now Closed
Notification for Acceptance: 15th December, 2023
Final PPT Submission: 22nd December, 2023
Final Presentation : The date will be announced soon
| User Design Track | ||
|---|---|---|
| No. | Title of the Submission | Name |
| 1 | A 4Ghz SRAM in 3nm with novel DFT scheme to improve at speed fault coverage | Sriharsha Enjapuri, Manish Trivedi, Deepesh Gujjar, Jaswinder Singh, Sandipan Sinha and Ramesh Halli |
| 2 | ATE Testing for Complex Memory at 7nm - DFT insights covering Peak-Power, Testing & Issues | Jaykumar Goraseeya and Raj Gandhi |
| 3 | TinyML System for Detecting Life-Threatening Ventricular Arrhythmias | Vipin Gautam, Sharad Sinha and Shitala Prasad |
| 4 | Modulating Free Layer of Magnetic Tunnel Junction : A Novel Approach for Energy-Efficient Computing in Memory | Alisha B , Dr. Tripti S. Warrier |
| 5 | Robust Noise Immune Inverting Schmitt Trigger for Radiation Exposed Environment | Aryan Kannaujiya, Ambika Prasad Shah |
| 6 | CRVPGen : C-Random verification programs for Processor design validation | Srinivasa Tipparaju, Rishna Patteri, Bijay Sharma and Karun Talari |
| 7 | Efficient Workload Optimization for CPU-GPU Co-Design in Intelligent Cyber-Physical Systems | Ashiqur Molla, Suraj Singh, Srijeeta Maity and Soumyajit Dey |
| 8 | Process Mismatch Tolerant Adaptive Read Assist for SRAM using Replica Bias Control | Ashish Kumar |
| 9 | Advance and Comprehensive Debug (Ad-Code) | Anmol Khatri, Soumik Mukherjee, Praveen Chinta and Lalit Arora |
| 10 | SPARC - An intelligent autonomous flow for power switch Selection, Placement, Auto Routing and Connectivity optimization | Subbash K P, Pardhu Pavan S and Vikash K T |
| 11 | Low-cost, Power IR drop consideration methodology for high contact resistance in advanced technologies nodes for robust memory design and accurate characterization. | Praveen Kumar Verma, Anuj Dhillon, Harshit Sharma and Vartul Sharma |
| 12 | Approximate CNN for Edge Computing | Abhinav K, Nalesh S and Kala S |
| 13 | FastMiner-Design and Implementation of FPGA accelerated Bitcoin Miner | Mayank Kabra, Harshita Gupta, Asmita Zjigyasu and Madhav Rao |
| 14 | System-Level Modeling for Real-Time DNN Inference on Edge Devices | Tom Jose and Deepak Shankar |
Important Link
Topics
Artificial Intelligence, Machine Learning and their Applications
AI Accelerators, Edge Computing, Approximate Computing, Autonomous Intelligence (ADAS), AI ethics.
Security and Safety
Functional Safety, Privacy, Cryptography, PUFs, TRNGs, Hardware Trojans, Trusted Computing, Network Security, Side-Channel and Fault Analysis and Countermeasures.
Analog and Mixed Signal Design
Analog Circuits for Various Applications, Data Converters, High Speed Interfaces, Power Management Circuits, Energy Harvesting Circuits & Systems, Circuits & Systems for AI-oriented Applications.
Sensors Circuits and Systems
Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Autocalibration Techniques, Wearable Electronics, Autonomous Sensors Systems.
Digital Integrated Circuits and Systems
Digital Circuits for Communication, Arithmetic Circuits, System-on-Chip Design, Network-on-Chip Design, Low-power Logic Design.
Power Electronics
High Power Circuits, Power Convertors, Power Optimization Techniques, Power Delivery Networks, Power Switches, High Voltage Circuits and Systems, Power Management for High Voltage Applications, Power Amplifiers.
Low power Digital Architectures
Next generation Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor, near- and sub-threshold systems, emerging applications, Digital circuits for intra-chip communication, clock distribution, variation-tolerant design, digital regulators and digital sensors.
RF Circuits and Systems
Transceiver Architectures, Short-Range Communication, IoT/IoE, WPAN, Ultra-Low Power Wireless Designs, Effective Spectrum Utilization, RF Power Amplifiers, RF Energy Harvesting.
Emerging Technologies and Devices
Quantum Computing, Neuromorphic Computing, Synaptic Devices, CMOS Technology and Devices, New Age Nano-Electronics, MEMS Devices, GaN and SiC Devices.
Test and Reliability
EMIR, Interconnect, Power Integrity-Signal Integrity (PISI), EMI/EMC Compatibility, Built-in Self-Test, Design for Test, Self-X (Awareness, Repair, Test), On-line Test, Fault Tolerance.
Embedded System Design
IoT Systems, Cyber-Physical Systems, Hardware/Software Co-design, Embe- dded Software, Embedded Operating Systems .
Architectures
Chip Architecture, Computer Architecture, High Performance Computing, Configurable Computing, (Embedded) FPGA, Memory Subsystems, In Memory Computing Systems.
Electronic Design Automation
Verification, Synthesis, Physical Design, Silicon Engineering, Just-in-time Synthesis, AI enabled algorithms, Formal Verification, Optimization.
Packaging and Interconnects
On-chip interconnects, 3D packaging, Wafer-level packaging, Interconnect Technologies.
Please Note
- All presentation submissions to User Design Track should be made electronically via the below submit button before the due date.
- Use provided presentation template only. You can download presentation template below.
- Maximum 10 slides can be used (including 1 title, 8 content and 1 thank you slide). All figures,references should be incorporated in this limit. The submission should be done in pdf format only.
- Presentation should clearly state the problem statement/novel ideas, proposed solution (results, and applications) of the contribution, silicon results if relevant/available.
- Use speaker notes to provide more details to the reviewer wherever necessary.
- Presentation exceeding the page limit or identifying the authors/organization will be rejected without review.
- Submissions will undergo a double-blind review.
- For selected presentation, authors need to submit recorded video of the presentation. Further details will be shared with the selected authors after acceptance notification.
