Student Research Forum
Name of students whose posters will be presented on 6th January:
| Title of the Paper |
Author |
| DAY 1 | |
| A Portable Artificial Intelligence Based Rehabilitation System | Amal Thomas K, Kaarmukilan S.P. and Soumyajit Poddar |
| Accelerated real time object detection through Raspberry Pi, PYNQ Z2 and Intel Movidius Neural Compute Stick | Kaarmukilan S.P., Amal Thomas K and Soumyajit Poddar |
| Self Aware Nature Inspired Approaches Ensuring Embedded Security | Krishnendu Guha |
| Bottleneck Crosstalk Minimisation in Two- and Three-Layer Channel Routing | Tarak Nath Mandal, Suvarthi Sarkar, Deborupa Roy, Ranjan Mehera, and Rajat Kumar Pal |
| Energy Efficient Spatio-Temporal Scheduling of Real-Time Tasks for Heterogeneous Reconfigurable Platforms |
Atanu Majumder |
| Accelerating Convolutional Neural Networks on FPGA | Kala S, Babita Jose, Jimson Mathew and Nalesh S |
| LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors | Sukarn Agarwal |
| A 3-Stage V-Band CMOS Low Noise Amplifier for IEEE 802.15 Wireless HDMI Applications | Andrew Roobert, D.Gracia Arul, Akash kannan K, Arunaggiri pandian K, Sai kumar T.S, Anugraha L and Thabasum aara S |
| Energy-efficient System Design for Hardware Accelerators | Mitali Sinha and Sujay Deb |
| Hardware IP Protection Using Logic Encryption and Watermarking | RAJIT KARMAKAR and Santanu Chattopadhyay |
| Dark Silicon Aware Network-on-Chip Buffer Management | Khushboo Rani |
| Logic in Memory Design using Spin Hall Effect Assisted Magnetic Tunnel Junction | Kanika Monga, Nitin Chaturvedi and S. Gurunarayanan |
| RISC-V based MPSoC System Development with NoC Architectures | Ayushi Dube and Soumya J. |
| Enhanced Detection and Prevention Techniques to Ensure Secured Hardware with Improved Performance Metrics | sree ranjani |
| AIVER: Asymmetrical Interleaved Vertical Edge Routing for Buffered Mesh On-Chip Networks | Rose George Kunthara, Neethu K, Rekha James, Simi Zerine Sleeba and John Jose |
| Bicubic Interpolation Based on LU Decomposition on FPGA for Low-Resolution IR images | Sahana K and Punithavathi Duraiswamy |
| Resilient and Cost-effective Architectures and Design Methodologies for Stacked Three Dimensional Integrated Circuits | Raviteja P Reddy |
| Designing Real-time Hybrid CMOS-OxRAM Based NVSRAM for Advanced Memory Applications | Swatilekha Majumdar, Sandeep Kaur Kingra and Manan Suri |
| MASTISK: Simulation framework for design exploration of neuromorphic hardware | Vivek Parmar, Sandeep Kaur Kingra, Tinish Bhattacharya, Devesh Joshi, Akanshu Gupta and Manan Suri |
| Parallel Itoh-Tsujii inversion algorithm for FPGA Platforms | Kalaiarasi M, Venkatasubramani VR, Rajaram S and Christina Grace A |
| Performance Improvement Techniques for Emerging Non-Volatile Memory Technologies | Supriya Chakraborty, Abhilash Garg and Manan Suri |
Name of students whose posters will be presented on 7th January:
| DAY 2 | |
| Energy-Efficient Point-of-Care Healthcare Diagnostics on Embedded Platforms | Narayani Bhatia, Khushal Sethi, Vivek Parmar, Shridu Verma and Manan Suri |
| Design and Implementation of An Accelerator Based on Extreme Learning Machine | Manoj Kumar, Umesh Lohani, Vivek Parmar, Ayan Ray and Manan Suri |
| New Generation of RF Circuits for 5G NR | Prateek Kumar Sharma and Nagarjuna Nallam |
| Low Leakage 10T SRAM with Improved Stability based on Modified Inverter for SoC Applications |
Krishna .R and Punithavathi Duraiswamy |
| A PCM Compact Model with Multilevel Resistance Capability |
Manoj Kumar and Manan Suri, |
| Verilog-A SPICE Model of PECVD SiO2 OTP Memory Device For Hardware Security Applications |
Ashwani Kumar, Abhilash Garg, Ahmed Shaban and Manan Suri |
| Tuning of ferroelectric polarization and its influence on dielectric switching, stiffness and device performance of piezo polymer PVDF | Ronit Ganguly, et. Al. |
| Doppler Ultrasound based Point-of-Care system for diagnosing Peripheral arterial diseases | Biswabandhu Jana |
| Investigating Graphene interconnects for next generation MQCA based low power nanomagnetic logic design |
Sanghamitra Debroy |
| Nanomagnetic Logic based Rebooting Computing Architectural Design Methodology and its Application on Resource Constrained AI |
Santhosh Sivasubramani and Amit Acharyya |
| VLSI Architecture Design Methodology for Unsupervised Underdetermined Blind Source Separation | Rashi Dutt and Amit Acharyya |
| STT-MRAM for Secure and Low Energy Hardware Architectures |
Ashwani Kumar, and Manan Suri |
| AI/ML Hardware Accelerated Voice Based Authentication System | Sai Sukruth Bezugam, Shubham Negi and Manan Suri |
| Applications of MOS Parametric Amplifier in RF Filters and Receivers |
Kamlesh Badiyari and Nagarjuna Nallam |
| Throughput and Energy Efficient Scheduling of Real-Time Tasks in Heterogeneous Computing Platforms |
Kalyan Baital and Amlan Chakrabarti |
| Design of Low Power Balun LNAs for NB-IoT and LoRaWAN Applications |
Shashank Tiwari and Jayanta Mukherjee |
| Efficient Techniques for Mitigating Issues in IC Layouts with Next Generation Lithography | Sudipta Paul, Pritha Banerjee and Susmita Sur-Kolay |
| A Novel Machine Learning Based Multi-Objective MemeticAlgorithm(ML-MOMA) for 3D IC floorplanning |
J.Shanthi and GraciaNirmala Rani |
| Energy efficient architectures for neuromorphic computing |
Anand Kumar Mukhopadhyay, Indrajit Chakrabarti, Mrigank Sharad |
| Hardware-Assisted Acceleration and Optimization of Algorithms in Computational Genomics |
Venkateshwarlu Yellaswamy Gudur, Sidharth Maheshwari, Rishad Shafik, Amit Acharyya1 |
| Architectures And Automation For Beyond-CMOS Technologies |
Debjyoti Bhattacharjee∗ and Anupam Chattopadhyay |