Electronic Design Automation & CAD :
Track Chairs : Chandan Karfa, IIT Guwahati & Sandeep Kumar Samal, Altera
Logic and behavioral synthesis; Logic mapping, simulation and formal verification; Physical design techniques; Post-route optimizations; memory compiler; Simulation tools for design verification; Static Timing Analysis and timing exceptions; Mixed-Signal simulations; EDA for sub-10nm nodes; Design for Debug (DFD) tools; Application of AI/ML in CAD for VLSI; Optimization of Placement and Routing, AI for placement and Routing, CAD for printed circuit boards (PCBs), CAD for secure chips. CAD for bio-inspired and neuromorphic systems. EDA and physical design tools, processes, methodologies, and flows, Design tools for analysis/ tolerance of variation, aging, and soft-errors, Design and maintenance of hard and soft IP blocks, EDA for non-traditional problems such as smart power grid and solar energy, EDA tools and methodologies for 3D integrations, and advanced packaging, Modeling and Simulation of Semiconductor Processes and Devices (TCAD), CAD for bio-inspired and neuromorphic systems, EDA tools, methodologies and applications for Photonics devices, circuit and system design, EDA for MEMS. Any other topics related design automation tools and methodologies.
Analog & Mixed Signal and RF circuits:
Track Chairs : Nagendra Krishnapura, IIT Madras & Aritra Banerjee, University of Illinois at Chicago
Deep nanoscale CMOS device modeling and simulation, multi-domain simulation, device/circuit-level reliability and variability, Devices for beyond CMOS, compact modeling and novel TCAD solutions. Amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Analog design at lower technology nodes, Analog Circuits for Various Applications, Data Converters, High Speed Interfaces. : RF, mm-Wave and THz transceivers, SoCs, and SiPs. frequency synthesizers, system architecture for 5G and 6G wireless, next generation systems for radar, sensing, and imaging. Reliability aspects in RFICs.
Embedded Systems, IoT, Cyber Physical Systems, Automotive Systems:
Track Chairs : Sharad Sinha, IIT Goa & Akash Kumar, Ruhr University Bochum
Embedded Systems Language (ESL); System-level design methodology; Concurrent interconnect; Networks-on-chip; Defect-tolerant architectures; Hardware/Software co-design and co-verification; Reconfigurable computing; Embedded multicores and multiprocessor system on a chip(MPSoC); Real-time embedded systems; Embedded software including Operating Systems, Firmware, Middleware; Communication, virtualization, encryption, compression, security, reliability; Embedded systems for automotive and Electric Vehicles (EVs); Edge intelligence; Artificial Intelligence of Things (AIoT); Design automation for IoT/CPS; MedTech devices and systems, RISC-V based systems. Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Auto Calibration Techniques, Wearable Electronics, flexible electronics, ultra-low power circuit techniques, circuits, AgriTech Systems, Robotics, and systems for IoT.
Verification and Reliability:
Track Chairs : Palkesh Jain, Qualcomm, India & Sayak Ray, Intel, USA
Simulation, formal verification, validation at different abstraction levels; All areas of DFT, ATE and BIST for digital designs, analog/mixed-signal IC’s, SoC’s, and memories, Post-silicon validation and debug; Delay test and speed-binning; Memory test, Reliability and fault tolerance; 2.5D/3D IC testing; Analog and Mixed-signal testing; Static/dynamic defect- and fault-recoverability; Learning-assisted testing; Statistical Testing; Variation-aware design. Hardware and software formal-, assertion-, and simulation-based design verification techniques, Test synthesis and synthesis for testability, Fault diagnosis, IDDQ test, novel test methods, effectiveness of test methods, fault models and ATPG, and DPPM prediction, SoC/IP testing strategies Design methodologies dealing with the link between testability and manufacturing, Hardware/software co-verification, Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs), Formal and semi-formal verification and validation techniques, Safety and security in verification and validation, New methods and tools supporting functional safety and security, Self-checking testbenches in analog verification, Any other topics related to design test and verification
Emerging Computing Concepts and Technologies
Track Chairs : Ishan Thakkar, Univ of Kentucky & Amit Saha, Inria, France
Cryogenics electronics for processors & sensors. Control & Readout quantum systems, Quantum Information processing systems, Quantum logic circuits, Quantum algorithms, Spin-based computing, Neuromorphic Computing, Stochastic Computing, Probabilistic Computing.
3DIC, Advanced Packaging:
Track Chairs : Jaydeep Kulkarni, University of Texas at Austin & Joycee Mekie, IIT Gandhinagar
Methodologies and tools for Wafer-level packaging, embedded chip packaging, 2.5D/3D integration, Silicon, SiC & Glass interposer, Thermal characterization and simulation, component, system and product level thermal management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu, wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level, Chiplets based Heterogeneous system design, SiP, micro-bump, high I/O thermocompression/hybrid bonding, fine-pitch/multi-layer RDL, printable interconnects, Innovative packaging technologies including 3D IC, 2.5D or interposer, and multi-chip module and their impact on system design, Design techniques, methodologies and flows for vertically integrated circuits/chips, Modeling and mitigation of device interactions for 3D ICs, Design of die-to-die interfaces in 3D/2.5D ICs, Design-for-testability and system-level design issues in 3D/2.5D, Die-package co-design, Any other topics related to circuit design, 3D integration and advanced packaging.
Hardware Security:
Track Chairs : Chester Rebeiro, IIT Madras & Shivam Bhasin, NTU, Singapore
Secure and trustworthy hardware, Side-channel Attack (SCA), Fault Attacks, and mitigation, Hardware IP Protection, Hardware Trojan attacks and mitigation, Security of IoT/CPS, Firmware and software security, Secure crypto, Automotive security, Hardware Design for Fully Homomorphic Encryptions, Security of Trusted Architectures, Polynomial Multipliers, Micro-architectural Security. Attacks and countermeasures including but not limited to side-channel attacks, reverse engineering, tampering, and Trojans, Hardware-based security primitives including PUFs, TRNGs and ciphers, Security, privacy, trust protocols, and trusted information flow, Ensuring trust using untrusted tools, IP, models and manufacturing , Secure hardware architectures Secure memory systems, Post-quantum security primitives, Security challenges and opportunities of emerging nanoscale devices, IoT and cyber-physical system security.
Hardware for Machine Learning & Artificial Intelligence:
Track Chairs : Viveka K R, IISc & Rajeev Balasubramonian, University of Utah
Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence, AI accelerator design, AI boosted circuits and systems for Brain Machine Interface, Intelligent storage, Memory Centric Accelerator Design, In-/Near memory computing circuits and architecture, Low power autonomous systems, Trusted Architectures for AI. Approximate Computing for AI acceleration. Multiplier Designs for high performance Computing, Activation Functions realization
Logic and Circuit Design:
Track Chairs : Sparsh Mittal, IIT Roorkee & Mashahiro Fujita, Tokyo, Japan
Next-generation digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced power and form factor; Near- and sub-threshold systems; Energy-efficient algorithms and applications; Energy-efficient storage systems; Digital circuits for intra-chip communication; Clock distribution; Low-power and robust design; Digital regulators and digital sensors; Low-power autonomous systems; Low-power communication; Advances in memory architectures for power reduction; Design for low-power FPGA, GPU, NPU and TPU. Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits, Approximate Computing.
Reconfigurable Computing & Processor Design:
Track Chairs : Sumit Mandal, IISc & Callie Hao, Georgia Institute of Technology
Autonomous/adaptable/reconfigurable systems and architectures, FPGA Accelerator Design, Placement & Routing of FPGA layout, High-performance, energy-efficient multi-core and many-core (heterogeneous) processor architectures including RISC-V. Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, networks-on-chip and Photonic Integrated Circuits & Optical Communication; Techniques for low-power, secure, and reliable processor architectures; Hardware support for processor virtualization; Real-life design challenges: case studies, trade-offs, retrospectives, HW/SW prototyping and emulation on FPGAs, Application driven heterogeneous computing platforms.
Power & Energy Management:
Track Chairs : Gajendranath Chaudhury, IITH & Amit Trivedi, University of Illinois at Chicago
Power management and control circuits, regulators; power converter ICs, energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators, Power management for automotive systems, battery management circuits and systems.