Conference Program - Detailed
| Tutorial Day 1 | 26 Feb 2022 | Saturday | ||||
|---|---|---|---|---|
|
Start (IST) |
End (IST) |
Duration |
Track 1 (Grand Pavilion) |
Track 2 (Auditorium 2) |
| 08:30 | 09:00 | 00:30 | Welcome/Registration to VLSID 2022 | |
| 09:00 | 09:30 | 00:30 | Opening Keynote Address | Prof. Ramgopal Rao, IIT Delhi | |
| 09:30 | 10:15 | 00:45 |
Brain Inspired Computing: The
Extraordinary Voyages from
Known to Unknown Worlds
Prof. Hai Li (Duke University) |
Event Cameras: From Biology to
Circuits to Applications
Prof Tobi Delbruck (INI/ETH Zurich/UZH) |
| 10:15 | 11:00 | 00:45 | ||
| 11:00 | 11:45 | 00:45 |
SoC Architectures for
accelerating AI Computing
Bharat Daga (Intel) |
Event-driven low-compute bioinspired processing for Edge Audio
Prof. Shih-Chii Liu (INI/ETH Zurich/UZH) |
| 11:45 | 12:30 | 00:45 | ||
| 12:30 | 13:30 | 01:00 | Lunch Break | |
| 13:30 | 14:15 | 00:45 |
AI for Quantum, quantum for AI Nagendra Nagaraja (Qpi Technology) |
On-Chip Memories - Challenges, Opportunities, and Recent Advances
Prof. Manan Suri (IIT-Delhi), Anuj Grover(IIIT-Delhi) |
| 14:15 | 15:00 | 00:45 | ||
| 15:00 | 15:45 | 00:45 |
Introduction to Memory technology & Products Kalyan Kavalipurapu and Venkat Bringivijayaraghavan, (Micron Technology) |
HBM System and Architecture for AI applications Manish Jain and Nikhil Raghavendra Rao (Rambus) |
| 15:45 | 16:30 | 00:45 | ||
| Tutorial Day 2 | 27 Feb 2022 | Sunday | ||||
|---|---|---|---|---|
|
Start (IST) |
End (IST) |
Duration |
Track 1 (Grand Pavilion) |
Track 2 (Auditorium 2) |
| 08:30 | 09:00 | 00:30 | Welcome/Registration to VLSID 2022 | |
| 09:00 | 09:30 | 00:30 | Keynote Address | Prof. Subhasis Chaudhuri, Director, IIT Bombay | |
| 09:30 | 10:15 | 00:45 |
Compound Semiconductor with particular focus on the increasing role of wide bandgap semiconductors in electronics Prof. Srabanti Chowdhury (Stanford) |
Beyond 5G & 6G Wireless
Communication
Tushar Vrind (Samsung) |
| 10:15 | 11:00 | 00:45 | ||
| 11:00 | 11:45 | 00:45 |
Heterogenous Integration (HI) using advanced packaging Arun Chandrasekhar & Rupesh Pothineni (Intel) |
Meeting Signal Integrity &
Reliability Requirements in
Automotive SoC Murali Mohan Thota (Texas Instruments) |
| 11:45 | 12:30 | 00:45 | ||
| 12:30 | 13:30 | 01:00 | Lunch Break | |
| 13:30 | 14:15 | 00:45 |
Building a multi protocol wireless
IoT Device
Tarun Chaplot (Silicon Labs) |
Security for Deep Learning – A Hardware Perspective Prof. Chip Hong Chang and Wang Si (NTU) |
| 14:15 | 15:00 | 00:45 | ||
| 15:00 | 15:45 | 00:45 |
Logic Design of a RISC-V
Microprocessor
Rajat Gupta (Sensonics), Yogesh Tripathi |
AI in Security – A Potential to Make
and Break a Secure Connected
World Prof. Debdeep Mukhopadhyay (IIT KGP) |
| 15:45 | 16:30 | 00:45 | ||
| Conference Day 1 | 28 Feb 2022 | Monday | ||||||
|---|---|---|---|---|---|---|
|
Start (IST) |
End (IST) |
Duration | Conference Agenda | |||
| 08:30 | 09:00 | 00:30 | Welcome/Registration to VLSID 2022 | |||
| 09:00 | 10:00 | 01:00 |
Inauguration Ceremony Sh. Ashwini Vaishnaw (Hon. Minister of Railways & IT), Sh. Rajeev Chandrasekhar (Hon. Minister of State for Electronics & IT) Sh. Basavaraj Bommai (Hon. Chief Minister, Karnataka), Dr. Ashwath Narayan (Minister of Electronics & IT, Karnataka) Other Government and Industry Dignitaries |
|||
| 10:00 | 10:10 | 00:10 | Conference Opening | |||
| 10:10 | 10:40 | 00:30 | Vision Address | Nick McKeown, SVP & GM, Network and Edge Group, Intel | |||
| 10:40 | 11:10 | 00:30 | Vision Address | H.-S. Philip Wong, Willard R. and Inez Kerr Bell Professor, Stanford | |||
| 11:10 | 12:10 | 01:00 |
Panel Discussion| Shaping the Future of Semiconductors in India
Prof. V. Kamakoti (IIT Madras), Raja Manickam (Tata Electronics), Sagar Sharma (Invest India), Dr. Satya Gupta (VLSI Society, India) Moderator: Nirmal John (Economic Times) |
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|
Start (IST) |
End (IST) |
Duration |
Track 1 (Grand Pavilion) |
Track 2 (Auditorium 2) |
Track 3 (Auditorium 3) |
Track 4 (Auditorium 4) |
| 12:10 | 13:10 | 01:00 |
Technical Papers Session: 1A Analog and Mixed signal |
Technical Papers Session: 1B Embedded Systems |
Technical Papers Session: 1C Electronics Design Automation |
Industry Forum Session: IF-1 |
| - | - | Session Chair : Maryam Shojaei Baghini, Indian Institute of Technology - Bombay | Session Chair : Nele Mentens, Leiden University, The Netherlands, and KU Leuven, Belgium | Session Chair : Taher Abbasi, Cadence Design Systems | Session Chair: N Venkatesh, Silicon Labs | |
| 12:10 | 12:30 | Invited Talk : Cheetah 2.0: Automated Framework to identify Low-precision Numerical Formats for DNN Accelerators Dr. Dhireesha Kudithipudi, University of Texas at San Antonio |
Invited Talk : AIOT based systems, Manoj Choudhary, IIT Jodhpur |
Invited Talk : Synthesis and Equivalence Checking Ankush Sood, Fellow, Cadence Design Systems |
IF1.1 EV Mobility Transformation with 48V Technologies Srinivas Kantheti, Analog Devices | |
| 12:30 | 12:50 | 1A.1 A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer ; Shraman Mukherjee, Sumantra Seth and Saurabh Saxena ; Texas Instruments India | 1B.1 A PC based Ultrasound back-end signal processor using Intel® Performance Primitives ; Jayaraj Kidav, Sreerama Pavan, Rajesh M and Navinkumar W ; NIELIT | 1C.1 Equivalence Checking of Non-Binary Combinational Netlist ; Aditi Singh ; Indian Institute of Technology, Kharagpur | IF1.2 Cadence Cerebrus Machine Learning Chip Design Optimization Delivers a PPA and Productivity Revolution Karthik Kandasamy, Cadence | |
| 12:50 | 13:10 | 1A.2 A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator with for High Bandwidth Memory parallel IOs ; Javed S. Gaggatur, Chandrashekhar Miryala and Komal Deshmukh ; Intel | 1B.2 Power and Energy Safe Real-Time Multi-Core Task Scheduling ; Kalyan Baital, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst and Xiaoqing Wen ; National Institute of Electronics and Information Technology, Kolkata Centre, Kolkata, India | 1C.2 Dynamic Variable Ordering during Algebraic Backward Rewriting for Formal Verification of Multipliers ; Jitendra Kumar and Asutosh Srivastava ; Jawaharlal Nehru University | IF1.3 Application and Trends of Functional Safety for Semiconductors Aarul Jain, NXP | |
| 13:10 | 14:00 | 00:50 | Lunch Break | |||
| 14:00 | 14:30 | 00:30 | Keynote | Joe Sawicki, Executive Vice President, Siemens Digital Industries Software | |||
| 14:30 | 15:00 | 00:30 | Keynote | Shankar Krishnamoorthy, GM, Silicon Realization Group, Corporate Staff, Synopsys | |||
| 15:00 | 16:00 | 01:00 |
Technical Papers Session: 2A
Analog and Mixed SIgnal |
Technical Papers Session 2B
Embedded Systems |
Technical Papers Session: 2C
Electronics Design Automation |
Industry Forum Session: IF-2 |
| - | - | Session Chair : Devarshi Mrinal Das, Indian Institute of Technology - Ropar, India | Session Chair : Mirjana Stojilovic, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland | Session Chair : Diana Goehringer, Dresden University of Technology (TU Dresden), Germany | Session Chair: Manish Goel, Samsung | |
| 15:00 | 15:20 | 2A.1 A 180-degree Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors ; Arpan Jain, Abhishek Pullela, Ashfakh Ali and Zia Abbas ; International Institute of Information Technology Hyderabad | 2B.1 Customizable Head-mounted Device for Detection of Eye Disorders using Virtual Reality ; Pawankumar Gururaj Yendigeri, Sai Anirudh Karre, Raghav Mittal, Raghu Reddy and Syed Azeemuddin ; Center for VLSI and Embedded Systems Technologies, IIIT Hyderabad | 2C.1 MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence ; Santanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy and Harikrishnan K ; Intel Technology India Pvt. Ltd. |
IF2.1 Next Era of Compute Shreyas Derashri, Imagination Technologies |
|
| 15:20 | 15:40 | 2A.2 A Real Time Multi-bit DAC Mismatch Estimation & Correction Technique for Wideband Continuous Time Sigma Delta Modulators ; Ankur Bal, Sharad Gupta and Rupesh Singh ; STMicroelectronics | 2B.2 Energy Aware Dynamic Load Balancer for Embedded Multi-core Systems ; Sachin Ramesh Pundkar, Surajit Pradeep Karmakar, Samir Kumar Mishra, Surendra Singh and Tushar Vrind ; Samsung Semiconductor India R&D Bengaluru | 2C.2 NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal Simulator ; Anjali Agrawal and Smruti R. Sarangi ; IIT Delhi | IF2.2 Data Analytics for High volume Semiconductor Manufacturing using AI/ML Harsh Desai, Synopsys | |
| 15:40 | 16:00 | 2A.3 A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method ; Santunu Sarangi, Indranil Som and Tarun Kanti Bhattacharyya ; Indian Institute of Technology Kharagpur | 2B.3 Energy Optimized Non-preemptive Scheduling of Real-Time Tasks with Precedence and Reliability Constraints ; Niraj Kumar and Arijit Mondal ; RGIPT Jais | 2C.3 Automated Debugger for Optimum Physical Clock Structure Targeting Minimal Latency ; Rushabh Shah, krishna agrawal, Anjaneyulu Gangisetty and Vishnu Bhaskari ; Digital Design Engineer, Intel Technology India Pvt. Ltd | IF2.3 Role of automotive radars and Emerging trends towards the future of autonomous driving Karthik Ramasubramanian, TI | |
| 16:00 | 16:10 | 00:10 | Closing Session | |||
| Conference Day 2 | 01 March 2022 | Tuesday | ||||||
|---|---|---|---|---|---|---|
|
Start (IST) |
End (IST) |
Duration | Conference Agenda | |||
| 09:00 | 09:30 | 00:30 | Vision Address | Suk Hwan Lim, Executive Vice President, Head of America S.LSI R&D Center, Samsung | |||
| 09:30 | 10:00 | 00:30 | Vision Address | Jason Cong, Volgenau Chair for Engineering Excellence and Director of VAST, UCLA | |||
|
Start (IST) |
End (IST) |
Duration |
Track 1 (Grand Pavilion) |
Track 2 (Auditorium 2) |
Track 3 (Auditorium 3) |
Track 4 (Auditorium 4) |
| 10:00 | 11:40 | 01:40 |
Technical Papers Session: 3A
Architecture |
Technical Papers Session 3B
Security and Safety |
Technical Papers Session: 3C
Electronics Design Automation |
Industry Forum Session: IF-3 |
| - | - | Session Chair : Srinivas Katkoori, University of South Florida, Florida, USA | Session Chair : Alpana Agarwal Thapar Institute of Engineering & Technology, India | Session Chair : Anand Balusu, IIT Roorkee, India | Session Chair: Rupa Kamoji, Synopsys | |
| 10:00 | 10:20 | 3A.1 Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework ; Aparna Nair M K, Police Manoj Kumar Reddy, Abijith Y.L., Venkatesh Rajagopalan and Soumya J ; BITS Pilani- Hyderabad Campus |
Invited Talk : Dream or reality? Automated prediction of cryptographic vulnerabilities during hardware design Ileana Buhan, Radboud University, Netherlands |
3C.1 Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions ; Ayan Chakraborty, Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar S and Lakshmanan Balasubramanian ; Indian Institute of Technology, Kharagpur |
IF3.1 SoC design optimization using Machine Learning Part 1 Rishubh Khurana, Qualcomm |
|
| 10:20 | 10:40 | 3A.2 Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet Architectures ; Sri Harsha Gade, Mitali Sinha, Madhur Kumar and Sujay Deb ; ARM Embedded Technologies Pvt. Ltd. | 3B.1 An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems ; Mohammad Ebrahimabadi, Mohamed Younis, Wassila Lalouani and Naghmeh Karimi ; University of Maryland Baltimore County | 3C.2 Stitch-avoiding Global Routing for Multiple E-Beam Lithography ; Kritanta Saha, Sudipta Paul, Pritha Banerjee and Susmita SurKolay ; Indian Statistical Institute |
IF3.2 SoC design optimization using Machine Learning Part 2 Lindsey Kostas, Qualcomm |
|
| 10:40 | 11:00 | 3A.3 Novel Circuit topology for configurable eDP and MIPI DPHY IO ; Sunil Kumar C R, Aruna kumar Lakya Srinivasamurthy and Sanjib Basu ; Mr | 3B.2 Static Malware Analysis using ELF features for Linux based IoT devices ; Akshara Ravi and Vivek Chaturvedi ; Indian Institute of Technology Palakkad | 3C.3 Robust Estimation of FPGA Resources and Performance from Python Level CNN Models ; Pingakshya Goswami, Masoud Shahshahani and Dinesh Bhatia ; University of Texas at Dallas |
IF3.3 Edge Intelligence in Wireless IoT
Sandeep Deshpande, Silicon Labs |
|
| 11:00 | 11:20 | 3A.4 MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication ; M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan and Madhura Purnaprajna ; PES University | 3B.3 HeapSafe: Securing Unprotected Heaps in RISC-V ; Asmit De and Swaroop Ghosh ; Pennsylvania State University | 3C.4 Identifying Combination of Defects and Unknown Defects on Semiconductor Wafers using Deep Learning and Hierarchical Reclustering ; Ankit Gupta, Adrita Barari, Damini, Keerthi Kiran Jagannathachar, Seungwoo Lee, Janghoon Oh, Jungha Kim and Minjoo Kim ; Samsung SSIR |
IF3.4 High Performance Computing Leadership, Umesh Nair, AMD |
|
| 11:20 | 11:40 | "Invited Talk : Next-Generation Deep-Learning Accelerators: From Hardware to System Sophia Shao, University of California, Berkeley" | 3B.3 SEVA: Structural Analysis based Security Evaluation of Sequential Locking ; Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman and SWARUP BHUNIA ; University of Florida | 3C.5 An Architectural support for Digital Microfluidic based Hot-Spot free Computing ; Sumanta Pyne ; National Institute of Technology Rourkela |
IF3.5 UST transforming the world's best companies throgh the power of technology, Subhodip Bandyopadhyay, UST Global |
|
| 11:40 | 12:10 | 00:30 | Keynote | Sanjive Agarwala, Corporate VP and GM, IP Group, Cadence | |||
| 12:10 | 13:10 | 01:00 |
Panel Discussion | Designeering Product Excellence (The Next Edge)
Naveed Sherwani (Rapid Silicon), Sunil M (Blue Semi), Sai Mopuri (Analog Devices) Moderator: Jaswinder Ahuja (Cadence) |
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| 13:10 | 14:00 | 00:50 | Lunch Break | |||
| 14:00 | 14:30 | 00:30 | Keynote | Andrew B Kahng, Distinguished Professor of CSE and ECE, UC San Diego | |||
| 14:30 | 16:10 | 01:40 |
Technical Papers Session: 4A
Special Session on Design Automation Conference (DAC) |
Technical Papers Session: 4B
Artificial Intelligence & ML |
Technical Papers Session: 4C
RF Circuits/Systems and Sensors |
Industry Forum Session: IF-4 |
| - | - | Session Chair : Preet Yadav, NXP Semiconductors | Session Chair : Francesco Regazzoni, University of Amsterdam, Amsterdam and University of Lugano, Switzerland | Session Chair : Mahima Arrawatia, Indian Institute of Technology - Guwahati, India | Session Chair: Viji Ranganna, Qualcomm | |
| 14:30 | 14:50 |
Invited Talk : 59th Design Automation Conference
Robert Oshana, Vice President, NXP Semiconductors |
"Invited Talk : Machine Learning Methods in Electronic Design Automation Sachin S. Sapatnekar, University of Minnesota" | "Invited Talk : Wireless Communications: SINR Ramesh Harjani, University of Minnesota" |
IF4.1 Silicon photonics-Opportunities and Challenges, Shivraj Dharne, GlobalFoundries |
|
| 14:50 | 15:10 | "4A.1 (58 DAC Best Paper Winner) Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" Hasan N. Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert Ou, Colin Schmidt, Samuel Steffl, John Wright, Ion Stoica, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao, University of California, Berkeley, Berkeley, CA; Jonathan Ragan-Kelley, Massachusetts Institute of Technology, Cambridge, MA | 4B.1 Hardware Accelerator for Capsule Network based Reinforcement Learning ; Dola Ram, Suraj Panwar and Kuruvilla Varghese ; Indian Institute of Science | 4C.1 A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing Applications ; Adithya S. Edakkadan, Kuntal Desai and Abhishek Srivastava ; International Institute of Information Technology, Hyderabad | IF4.2 Challenges in design of high megapixel mobile cameras Venkatesh Teeka, Samsung | |
| 15:10 | 15:30 | 4A.2 A Compute-in-Memory Architecture Compatible with 3D NAND Flash that Parallelly Activates Multi-Layers Liang Zhao, Chu Yan, Fan Yang, Shifan Gao Yi Zhao, Zhejiang University, Hangzhou, China; Gabriel Rosca, Dan Manea, Zhichao Lu, Hefei Reliance Memory Ltd., Hefei, China | 4B.2 SCENIC: An Area and Energy-Efficient CNN-based Hardware Accelerator for Discernable Classification of Brain Pathologies using MRI ; Bodepu Sai Tirumala Naidu, Shreya Biswas, Rounak Chatterjee, Sayak Mandal, Srijan Pratihar, Ayan Chatterjee, Arnab Raha, Amitava Mukherjee and Janet Paluh ; SandLogic Technologies | 4C.2 A Low Phase Noise 30 GHz Oscillator Topology for Resonant-Fin-Transistors Based High-Q On-chip Resonators in 14 nm Technology ; Abhishek Srivastava and Shreyas Sen ; IIIT Hyderabad |
IF4.3 Enabling Industry Trends: Smart Mobility | Power & Energy | IoT & 5G Ravi Koodli Nagaraja, ST Microelectronics |
|
| 15:30 | 15:50 | 4A.3 DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks Ahmet F. Budak, David Pan, Nan Sun, The University of Texas at Austin, Austin, TX; Prateek Bhansali, Chandramouli V. Kashyap, Intel Corporation, Hillsboro, OR; Bo Liu, University of Glasgow, Glasgow, United Kingdom | 4B.3 Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks ; Neelam Surana, Pramod Kumar Bharti, Bachu Varun Tej and Joycee Mekie ; IIT Gandhinagar | 4C.3 Design Methodology of Low Phase Noise mmWave Oscillator with Partial Cancellation of Static Capacitance of High-Q On-chip MEMS Resonator ; Ashish Papreja, Mantha Venkata Surya Sresthavadhani and Abhishek Srivastava ; IIIT Hyderabad |
IF4.4 Silicon Catalyzing Computing, Communication and Cognitive Convergence – Sustainably Ish Dham, Arm |
|
| 15:50 | 16:10 | 4A.4 NAAS: Neural Accelerator Architecture Search Yujun Lin, Song Han, Massachusetts Institute of Technology, Cambridge, MA; Mengtian Yang, Shanghai Jiao Tong University, Shanghai, China | 4B.4 Towards a Fully Autonomous UAV Controller for Moving Platform Detection and Landing ; Michalis Piponidis, Panayiotis Aristodemou and Theocharis Theocharides ; University of Cyprus | 4C.4 An event driven approximate bio-electrical model generating surface electromyography RMS features ; Vinay C. K, Vikas Vazhayil and Madhav Rao ; Pennsylvania State University |
IF4.5 Trends and Challenges in 2.5D/3D integration for next generation chiplets
Tanay Karnik, Intel |
|
| 16:10 | 17:40 | 01:30 |
Awards Session Presided by | Sonam Wangchuk, Himalayan Institute of Alternative Ladakh |
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| Conference Day 3 | 02 March 2022 | Wednesday | ||||||
|---|---|---|---|---|---|---|
|
Start (IST) |
End (IST) |
Duration | Conference Agenda | |||
| 09:00 | 09:30 | 00:30 | Keynote | Ken Wiseman, Vice President Technology, Qualcomm | |||
| 09:30 | 10:00 | 00:30 | Keynote | Daisy Chittilapilly, President, CISCO India and SAARC | |||
|
Start (IST) |
End (IST) |
Duration |
Track 1 (Grand Pavilion) |
Track 2 (Auditorium 2) |
Track 3 (Auditorium 3) |
Track 4 (Auditorium 4) |
| 10:00 | 11:40 | 01:40 |
Technical Papers Session: 5A
Digital Design |
Technical Papers Session: 5B
Test/Reliability and Power Electronics |
Student Research Forum: SRF-1 | User Design Track: UDT-1 |
| - | - | Session Chair : Manish Hooda, Semi-conductor Laboratory | Session Chair : Souvik Basu, Qualcomm | Session Chair : Nishit Gupta, Meity | Session Chair : Santhosh Adinarayan, Analog Devices | |
| 10:00 | 10:20 |
Invited Talk : Composing FPGA-Based Architectures and Techniques for Compute and Data-Intensive Applications on Embedded Platforms Darshika G. Perera, University of Colorado |
5B.1 Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform ; Krishnendu Guha and Amlan Chakrabarti ; University of Florida |
Invited talk: Invited talk: Very Large Scale Integrated Research Debdeep Mukhopadhyay, IIT Kharagpur |
UDT-1.1 Design Intent: A Tool to Enhance Productivity and Quality in Custom Memory Designs "Ashvani Kumar Mishra, Anuj Dhillon, Ishita Dhawan, Shafquat Jahan AHMED, Hitesh Chawla and Tarun Handa STMicroelectronics,India" | |
| 10:20 | 10:40 | 5A.1 Approximate Adders for Deep Neural Network Accelerators ; Raghuram S and Shashank N ; MSRIT | 5B.2 Pulse-width modulation technique for generation of multiple analog voltages for on-chip calibration ; Rajath Vasudevamurthy ; B.M.S. College of Engineering | 1.1 Impact of Polarization Switching on Hysteresis-Free and Hysteresis based Ferroelectric FET ; Nitanshu Chauhan, Sudeb Dasgupta and Anand Bulusu ; IIT Roorkee | UDT-1.2 Optimizing SoC Simulation Time by >10X Using Instruction Accurate Behavioral Model of Processor "Ravi Mangal and Alagendran Chidambaram Micron Technology, India" | |
| 10:40 | 11:00 | 5A.2 40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode ; Kedar Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey and Daniel Noblet ; STMicroelectronics Pvt. Ltd. | 5B.3 Easily Verifiable Design of Non-Scan Sequential Machines for Conformance Checking ; Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh Das and Bhargab B. Bhattacharya ; Indian Institute of Technology Kharagpur | 1.2 Improving Lifetime of Non Volatile Memory Caches ; Sivakumar S and John Jose ; IIT Guwahati | UDT-1.3 I/O Constraints Optimization: Shift Left using ML "Lekshmi C, Anmol Khatri, Shivangi Gupta, Sourav Saha, Raj Yadav and Rakshit Bazaz Intel India Pvt Ltd" | |
| 11:00 | 11:20 | 5A.3 Low Power and Area Efficient Approximate 2D-DCT Architecture for Wireless Capsule Endoscopy ; Vaibhavi Solanki, Rahul Ranjan Kumar, Praveen Ghagare and Anand Darji ; Sardar Vallabhbhai National Institute of Technology at Surat | 5B.3 Parasitic Interactions with Intermediate Substrates and Methods to Mitigate their Impact: A Case Study in Voltage Protection ICs ; Srinivasa Prasad Soundararajan, Harry Gee and Adam Whitworth ; ONSEMI | 1.3 Self Aware Nature Inspired Approaches Ensuring Embedded Security ; Krishnendu Guha ; University of Florida | UDT-1.4 A Parallel Elliptic Curve Crypto processor for FPGA platforms "Kalaiarasi M, Venkatasubramani VR and Rajaram S Thiagarajar College of Engneering, Anna University" | |
| 11:20 | 11:40 | 5A.4 Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI ; Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Dhori and Harsh Rawat ; IIT Delhi | 5B.4 A High Voltage Level Shifter for Automotive Buck Converter with a Fast Transient Response ; Anupama Deo, Ashis Maity and Amit Patra ; Indian Institute of Technology, Kharagpur | 1.4 Reduced Retention Time Voltage gated Spin Orbit Torque Random Access Memory True random number generator for On-chip designs ; Alisha P.B and Dr. Tripti S. Warrier ; Cochin university of science and technology | UDT-1.5 A methodology to overcome logical DRAM memory model limitations using an SV-RNM based solution including TX/RX equalization to verify Read/Write Trainings of Memory Ips "Mahesh Venkata Thorata, Subhadip Hazra, Azarathamma S and Varun Warrier Rambus, India" | |
| 11:40 | 12:10 | 00:30 | Keynote | Manish Kothari, VP. Silicon Labs | |||
| 12:10 | 13:10 | 01:00 |
Panel Discussion | Building Semiconductor Research & Talent
Navakant Bhat (IISc), Rituparna Mandal (MediaTek), Sanjay Gupta (NXP Semiconductors), Sunita Verma (MeitY) Moderator: Vivek Sharma (ST Micro Electronics) |
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| 13:10 | 14:00 | 00:50 | Lunch Break | |||
| 14:00 | 15:00 | 01:00 | Start-up Showcase | Product/Technology Demonstration by 5 Most Promising Startups | |||
| 15:00 | 16:40 | 01:40 |
Technical Papers Session: 6A
Packaging & Emerging Technologies |
Technical Papers Session: 6B
Emerging Technologies and Devices |
Student Research Forum: SRF-2 | User Design Track: UDT-2 |
| - | - | Session Chair : Sujay Deb, IIIT, Delhi | Session Chair : Elena-Ioana Vătăjelu, Université Grenoble Alpes, France | Session Chair : John Jose, IIT Guwahati | Session Chair : Subhash Chintamaneni, Micron | |
| 15:00 | 15:20 |
Invited Talk : How to predict Silicon process behaviour in IC Fabrication,
Sudhanshu S. Jamuar, IIIT Delhi |
"Invited Talk: Emerging Memory based Processing-in-Memory Architecture for Low-Power Deep Learning Fan Chen, Indiana University Bloomington, USA" | Invited talk: Sudeb Dasgupta, IIT-Roorkee | UDT-2.1 End2End FPGA Prototyping : Flexible, Configurable & Scalable solution for SW development, Integration & System level Validation | |
| 15:20 | 15:40 | 6A.1 A Soft RISC-V Vector Processor for Edge-AI ; Naveen Chander and Kuruvilla Varghese ; Indian Institute of Science | 6B.1 Threshold Voltage Modeling of Negative Capacitance Double Gate TFET ; SHIKHA U S, Rekha K. James, Sumi Baby, Anju Pradeep and Jobymol Jacob ; Cochin University of Science and Technology | 2.1 Performance-aware Design-space Optimization and Attack Mitigation for Emerging Heterogeneous Architectures ; Mitali Sinha ; IIIT Delhi | UDT-2.2 Robust Detection of Leakage Currents at Cell and Device Levels "Akshita Bansal, Jerome Lescot and Atul Bhargava ST Microelectronics, India" | |
| 15:40 | 16:00 | 6A.2 Design of 8-bit Dadda Multiplier using Gate Level Approximate 4:2 Compressor ; KATTEKOLA NARESH, Shubhankar Majumdar and Y Padma Sai ; NIT Meghalaya | 6B.2 Design Optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-FinFET for Mid-Band 5G Application ; Jyoti Patel, Shashank Banchor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu and Sudeb Dasgupta ; Research Scholar, IIT Roorkee | 2.2 Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms ; Surajit Das ; IIT Guwahati | UDT-2.3 Enabling In-Memory Computing with New Energy Efficient Assist Sense Amplifier for Boolean Computation in SRAM Array "Kavitha S, Santosh Kumar Vishvakarma and Bhupendra Singh Reniwal Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram, India" | |
| 16:00 | 16:20 | 6A.3 DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification ; Mahabubul Alam and Swaroop Ghosh ; Pennsylvania State University | 6B.3 How Good Silicon Oxide-based Memristor Can be ? ; Mani Shankar Yadav, Avinash Kumar Gupta, Kanupriya Varshney and Brajesh Rawat ; IIT ROPAR | 2.3 Design of Hardware Accelerators: Convolution Neural Network- based Image Inference Engines - Focusing on Performance and Energy- Efficiency Improvement ; Deepika S and Arunachalam V ; Vellore Institute of Technology | UDT-2.4 Multi-Objective Optimization of TFET with Machine Learning Methods "Charumathi V, Dr. Balamurugan N.B., Dr. Suguna M., Hemalatha M and Dr. Sriram Kumar D. Thiagarajar College of Engneering, Anna University" | |
| 16:20 | 16:40 | 6A.4 Image Completion using a Sparse Probabilistic Spin Logic Network ; AMINA HAROON and Sneh Saurabh ; | 6B.4 Role of Interface Trap Charges in the Performance of Monolayer and Bilayer MoS2-based Field-Effect Transistors ; Akhilesh Rawat, Anjali Goel and Brajesh Rawat ; Indian Institute of Technology Ropar | 2.4 Design and construction of Precision and Sliding Pulse Generator ; Ajit Tukaram Patil, Prakash Pandurang Vaidya and Asma Parveen Imran Siddavatam ; Vivekanand Education Society's Institute of Technology | UDT-2.5 CLE Layout Development Methodologies to Enhance Productivity of custom I/Os' and Test-Chip design "Varun Kumar Dwivedi ST Microelectronics, India" | |
| 16:40 | 16:55 | 00:15 | Closing Session | |||
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