Awards:
| Award | Cash Prize |
|---|---|
|
A.K. Choudhary Best Paper Award |
50000 |
|
Nripendra Nath Biswas Best Student Paper Award
|
35000 |
|
Naresh Malipeddy Honorable Mention Award
|
20000 |
Accepted papers:
| Submission ID | Title | Authors |
|---|---|---|
| 5 | Approximate Adders for Deep Neural Network Accelerators | Raghuram S and Shashank N |
| 9 | An event driven approximate bio-electrical model generating surface electromyography RMS features | Vinay C. K, Vikas Vazhayil and Madhav Rao |
| 16 | 40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode | Kedar Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey and Daniel Noblet |
| 22 | Hardware Accelerator for Capsule Network based Reinforcement Learning | Dola Ram, Suraj Panwar and Kuruvilla Varghese |
| 23 | Equivalence Checking of Non-Binary Combinational Netlist | Aditi Singh |
| 24 | Dynamic Variable Ordering during Algebraic Backward Rewriting for Formal Verification of Multipliers | Jitendra Kumar and Asutosh Srivastava |
| 25 | A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer | Shraman Mukherjee, Sumantra Seth and Saurabh Saxena |
| 30 | MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence | Santanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy and Harikrishnan K |
| 32 | Threshold Voltage Modeling of Negative Capacitance Double Gate TFET | SHIKHA U S, Rekha K. James, Sumi Baby, Anju Pradeep and Jobymol Jacob |
| 41 | NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal Simulator | Anjali Agrawal and Smruti R. Sarangi |
| 43 | Automated Debugger for Optimum Physical Clock Structure Targeting Minimal Latency | Rushabh Shah, krishna agrawal, Anjaneyulu Gangisetty and Vishnu Bhaskari |
| 59 | An Architectural support for Digital Microfluidic based Hot-Spot free Computing | Sumanta Pyne |
| 62 | An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems | Mohammad Ebrahimabadi, Mohamed Younis, Wassila Lalouani and Naghmeh Karimi |
| 73 | A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator with for High Bandwidth Memory parallel IOs | Javed S. Gaggatur, Chandrashekhar Miryala and Komal Deshmukh |
| 77 | A 180-degree Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors | Arpan Jain, Abhishek Pullela, Ashfakh Ali and Zia Abbas |
| 88 | Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework | Aparna Nair M K, Police Manoj Kumar Reddy, Abijith Y.L., Venkatesh Rajagopalan and Soumya J |
| 92 | A PC based Ultrasound back-end signal processor using Intel® Performance Primitives | Jayaraj Kidav, Sreerama Pavan, Rajesh M and Navinkumar W |
| 108 | A Real Time Multi-bit DAC Mismatch Estimation & Correction Technique for Wideband Continuous Time Sigma Delta Modulators | Ankur Bal, Sharad Gupta and Rupesh Singh |
| 115 | Low Power and Area Efficient Approximate 2D-DCT Architecture for Wireless Capsule Endoscopy | Vaibhavi Solanki, Rahul Ranjan Kumar, Praveen Ghagare and Anand Darji |
| 132 | Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform | Krishnendu Guha and Amlan Chakrabarti |
| 134 | Power and Energy Safe Real-Time Multi-Core Task Scheduling | Kalyan Baital, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst and Xiaoqing Wen |
| 137 | Parasitic Interactions with Intermediate Substrates and Methods to Mitigate their Impact: A Case Study in Voltage Protection ICs | Srinivasa Prasad Soundararajan, Harry Gee and Adam Whitworth |
| 142 | Customizable Head-mounted Device for Detection of Eye Disorders using Virtual Reality | Pawankumar Gururaj Yendigeri, Sai Anirudh Karre, Raghav Mittal, Raghu Reddy and Syed Azeemuddin |
| 144 | Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet Architectures | Sri Harsha Gade, Mitali Sinha, Madhur Kumar and Sujay Deb |
| 155 | Pulse-width modulation technique for generation of multiple analog voltages for on-chip calibration | Rajath Vasudevamurthy |
| 160 | Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions | Ayan Chakraborty, Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar S and Lakshmanan Balasubramanian |
| 161 | Static Malware Analysis using ELF features for Linux based IoT devices | Akshara Ravi and Vivek Chaturvedi |
| 177 | A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing Applications | Adithya S. Edakkadan, Kuntal Desai and Abhishek Srivastava |
| 183 | Stitch-avoiding Global Routing for Multiple E-Beam Lithography | Kritanta Saha, Sudipta Paul, Pritha Banerjee and Susmita SurKolay |
| 199 | Novel Circuit topology for configurable eDP and MIPI DPHY IO | Sunil Kumar C R, Aruna kumar Lakya Srinivasamurthy and Sanjib Basu |
| 207 | Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI | Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Dhori and Harsh Rawat |
| 208 | A Low Phase Noise 30 GHz Oscillator Topology for Resonant-Fin-Transistors Based High-Q On-chip Resonators in 14 nm Technology | Abhishek Srivastava and Shreyas Sen |
| 216 | Design Optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-FinFET for Mid-Band 5G Application | Jyoti Patel, Shashank Banchor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu and Sudeb Dasgupta |
| 218 | How Good Silicon Oxide-based Memristor Can be ? | Mani Shankar Yadav, Avinash Kumar Gupta, Kanupriya Varshney and Brajesh Rawat |
| 222 | Role of Interface Trap Charges in the Performance of Monolayer and Bilayer MoS2-based Field-Effect Transistors | Akhilesh Rawat, Anjali Goel and Brajesh Rawat |
| 225 | SCENIC: An Area and Energy-Efficient CNN-based Hardware Accelerator for Discernable Classification of Brain Pathologies using MRI | Bodepu Sai Tirumala Naidu, Shreya Biswas, Rounak Chatterjee, Sayak Mandal, Srijan Pratihar, Ayan Chatterjee, Arnab Raha, Amitava Mukherjee and Janet Paluh |
| 226 | Design Methodology of Low Phase Noise mmWave Oscillator with Partial Cancellation of Static Capacitance of High-Q On-chip MEMS Resonator | Ashish Papreja, Mantha Venkata Surya Sresthavadhani and Abhishek Srivastava |
| 228 | DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification | Mahabubul Alam and Swaroop Ghosh |
| 229 | HeapSafe: Securing Unprotected Heaps in RISC-V | Asmit De and Swaroop Ghosh |
| 234 | SEVA: Structural Analysis based Security Evaluation of Sequential Locking | Abdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman and Swarup Bhunia |
| 236 | MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication | M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan and Madhura Purnaprajna |
| 245 | Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks | Neelam Surana, Pramod Kumar Bharti, Bachu Varun Tej and Joycee Mekie |
| 255 | Image Completion using a Sparse Probabilistic Spin Logic Network | Amina Haroon and Sneh Saurabh |
| 256 | Energy Aware Dynamic Load Balancer for Embedded Multi-core Systems | Sachin Ramesh Pundkar, Surajit Pradeep Karmakar, Samir Kumar Mishra, Surendra Singh and Tushar Vrind |
| 261 | A Soft RISC-V Vector Processor for Edge-AI | Naveen Chander and Kuruvilla Varghese |
| 263 | Design of 8-bit Dadda Multiplier using Gate Level Approximate 4:2 Compressor | Kattekola Naresh, Shubhankar Majumdar and Y Padma Sai |
| 267 | Identifying Combination of Defects and Unknown Defects on Semiconductor Wafers using Deep Learning and Hierarchical Reclustering | Ankit Gupta, Adrita Barari, Damini, Keerthi Kiran Jagannathachar, Seungwoo Lee, Janghoon Oh, Jungha Kim and Minjoo Kim |
| 269 | Easily Verifiable Design of Non-Scan Sequential Machines for Conformance Checking | Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh Das and Bhargab B. Bhattacharya |
| 274 | Energy Optimized Non-preemptive Scheduling of Real-Time Tasks with Precedence and Reliability Constraints | Niraj Kumar and Arijit Mondal |
| 276 | A High Voltage Level Shifter for Automotive Buck Converter with a Fast Transient Response | Anupama Deo, Ashis Maity and Amit Patra |
| 277 | A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method | Santunu Sarangi, Indranil Som and Tarun Kanti Bhattacharyya |
| 285 | Towards a Fully Autonomous UAV Controller for Moving Platform Detection and Landing | Michalis Piponidis, Panayiotis Aristodemou and Theocharis Theocharides |
| 291 | Robust Estimation of FPGA Resources and Performance from Python Level CNN Models | Pingakshya Goswami, Masoud Shahshahani and Dinesh Bhatia |
Author Guidelines:
1. Camera Ready Paper Instruction:
2. Paper presentation:
a. Paper Presentation Template
b. Paper Video Instruction – Duration 10 – 17 mins
3. Poster presentation:
a. Poster Presentation Template
b. Poster Video Instruction – Duration 4 – 5 mins
4. Video Recording Instruction:
Important Dates:
✓ Deadline for Full Paper Submission :
31-Oct-21
✓ Notification for Acceptance :
23-Dec-21
✓ Deadline for Submission of Camera-ready Paper :
23-Jan-22
✓ Conference :
26 Feb to 02 Mar 2022
✓ Deadline for Full Paper Submission : 31-Oct-21
✓ Notification for Acceptance : 23-Dec-21
✓ Deadline for Submission of Camera-ready Paper : 23-Jan-22
✓ Conference : 26 Feb to 02 Mar 2022
Please Note:
All Regular papers must be in PDF format only, with save-able text.
- Each paper must be no more than 6 pages (including the abstract, figures, tables, and references), double-columned in IEEE Format
- Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person.
- Submissions not adhering to these rules, or determined to be previously published or simultaneously submitted to another conference, or journal, will be summarily rejected.
- The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules.
Important: Final camera-ready versions must be identical to the submitted papers with the following exceptions; inclusion of author names/affiliation, correction of identified errors, addressing reviewer-demanded changes. No other modifications of any kind are allowed including modification of title, change of the author list, reformatting, restyling, rephrasing, removing figures/results/text, etc.
For questions Contant: [email protected]
CFP Topics
Artificial Intelligence, Machine Learning and their Applications
AI Accelerators, Edge Computing, Approximate Computing, Autonomous Intelligence (ADAS), AI ethics
Security and Safety
Functional Safety, Privacy, Cryptography, PUFs, TRNGs, Hardware Trojans, Trusted Computing, Network Security, Side-Channel and Fault Analysis and Countermeasures
Analog and Mixed Signal Design
Analog Circuits for Various Applications, Data Converters, High Speed Interfaces, Power Management Circuits, Energy Harvesting Circuits & Systems, Circuits & Systems for AI-oriented Applications
Sensors Circuits and Systems
Sensor Interfacing, Instrumentation, Biomedical Circuits and Healthcare Systems, Low Noise Circuits, EMI Immune Design, Autocalibration Techniques, Wearable Electronics, Autonomous Sensors Systems
Digital Integrated Circuits and Systems
Digital Circuits for Communication, Arithmetic Circuits, System-on-Chip Design, Network-on-Chip Design, Low-power Logic Design
Power Electronics
High Power Circuits, Power Convertors, Power Optimization Techniques, Power Delivery Networks, Power Switches, High Voltage Circuits and Systems, Power Management for High Voltage Applications, Power Amplifiers
Emerging Technologies and Devices
Quantum Computing, Neuromorphic Computing, Synaptic Devices, CMOS Technology and Devices, New Age Nano-Electronics, MEMS Devices, GaN and SiC Devices
RF Circuits and Systems
Transceiver Architectures, Short-Range Communication, IoT/IoE, WPAN, Ultra-Low Power Wireless Designs, Effective Spectrum Utilization, RF Power Amplifiers, RF Energy Harvesting
Embedded System Design
IoT Systems, Cyber-Physical Systems, Hardware/Software Co-design, Embedded Software, Embedded Operating Systems
Test and Reliability
EMIR, Interconnect, Power Integrity-Signal Integrity (PISI), EMI/EMC Compatibility, Built-in Self-Test, Design for Test, Self-X (Awareness, Repair, Test), On-line Test, Fault Tolerance
Electronic Design Automation
Verification, Synthesis, Physical Design, Silicon Engineering, Just-in-time Synthesis, AI enabled algorithms, Formal Verification, Optimization
Architectures
Chip Architecture, Computer Architecture, High Performance Computing, Configurable Computing, (Embedded) FPGA, Memory Subsystems, In Memory Computing Systems
Packaging and Interconnects
On-chip interconnects, 3D packaging, Wafer-level packaging, Interconnect Technologies
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