Tutorial Day - 2 | 9th Jan, 2023 | Monday
2.1.1 CXL – High Speed Cache Coherent Interconnect
Speakers
- Sridhar Muthrasanallur, Principal Engineer, Intel
- Sunita Jain, Principal Member Technical Staff (PMTS), AMD
Abstract
Compute Express Link™ (CXL™) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion and Accelerators.
The CXL Consortium is an open industry standard group formed to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data centre accelerators and other high-speed enhancements. The continuing explosion of data and data-centric applications is driving heterogenous compute and memory centric architectures. CXL is continuing to gain momentum with product announcements from member companies.
This tutorial will focus on the CXL standard covering
- CXL introduction and evolution till v3.0 specifications
- CXL memory use cases & challenges
- Coherency protocol deep dive highlighting newer features in CXL v3.0
Speakers Bio
Sunita Jain
Sunita Jain is a Principal Member of Technical Staff at AMD. She joined AMD through Xilinx acquisition. During her sixteen-year career in Xilinx/AMD, Sunita’s efforts are mainly focused on designing system architectures. Her expertise spans across applications over PCI Express, Cache Coherent Interconnect for Accelerators (CCIX) and most recently Compute Express Link (CXL).
Sunita holds a M Tech. in VLSI from IIT Madras and has four granted US patents.
Sridhar Muthrasanallur
Sridhar Muthrasanallur is an I/O standards architect in Intel Corporation, with more than 2 decodes of industry experience. He is currently working on standards definition of CXL fabric and UCIe die-die interconnect. He has breath of Systems and SoC architecture expertise and has successfully contributed to many shipping platforms across Servers and Client PCs.
2.1.2 Disaggregation Technology
Speaker
- Biswajit P, Senior Principal Engineer, Intel, Bangalore
- Deboleena S, Principal Engineer, Intel, Bangalore
- Rupesh P, Principal Engineer, Intel, Bangalore
Motivation
The purpose of this tutorial is to assess Disaggregation State of Union across key technology pillars to ensure high quality products. Checkpoint the promises with current product realities and bring-out primary areas of key technologies to realize 10X product scale in next 5 years. The motivation is to ignite the thinking process with the VLSI design community on innovations needed on disaggregation architecture, packaging, choices of technology nodes, die size and TFM on top of the strategy and share the current state of art disaggregation technologies.
Objectives
The objectives of this tutorial are listed as following.
- Present state-of-the-art knowledge on the design and development of disaggregation technologies, circuits, and tools.
- Summarize the realistic application advances leveraging on the scalable disaggregation technologies
- Present latest state of art findings on design automation flows to ensure quality SOC augmenting disaggregation technologies.
Abstract
Disaggregation is one of the key strategies to bring forth rapid product innovation at scale by using smart combination of: Chiplet Ecosystem, Advanced Packaging, Compute Capacity, Memory Bandwidth, and unparalleled IP portfolio. We assess the opportunities Disaggregation promises to bring and check-point current state-of the union across key pillars towards the vision. Wealth of advancement and technological ideas are tongue-n-cheeked with Product, Packaging and Ecosystem realities. Goal is to cover below topics and brainstorm with technical community
Tutorial Plan
- Introduction [30 min]
- Realizing the benefits of disaggregation [15 min]
- Architectural considerations [30 min]
- SoC Design Challenges [45 min]
- Tools, flows and Methodology [30 min]
Speakers Bio
Biswajit Patra
Dr. Biswajit Patra, has been working in Intel India as “Sr. Principal Engineer” focusing on low power & high performance design & high-volume SOC in advance technology nodes for AI/ML, heterogeneous and mobile compute. Previously worked as “Principal Engineer” in SOC physical design at Qualcomm, Bangalore, India. He has completed his PhD in computer science and M. Tech in ECE from Calcutta University & effective leadership & management from The Eli Broad College of Business, Michigan state university.
His technical domain expertise includes mission critical functionalities like 3D IC, SOC power delivery design, SOC lifetime reliability, PCB-Package-SOC co-optimization, low power high performance SOC design and thermal modelling in multiple first-time-create strategic and business critical products deploying high performance XPUs & advance technology nodes for mobile, laptop, exascale Computing & AI supercomputer. During his career, he has authored more than 40 papers in national and international journals /conference in low power SOC design.
Deboleena Sakalley
Deboleena Sakalley joined Intel in Dec 2019 as a Principal Engineer. Prior to joining Intel, she has worked in Xilinx, Freescale Semiconductors and STMicroelectronics. She has over 20 years of experience in front end IP/SoC design and architecture. At Intel, she is a part of the team working on the UCIe Die-to-Die stack.
She has filed 18 patents till date with 15 patents already granted and rest in pipeline. She has done her Btech in EE from Indian Institute of Technology, Bombay. She has a 15 year old son and a 13 year old daughter. She is an avid reader and loves to read in her free time.
Rupesh P
Rupesh is a principal engineer in NEX silicon Group at intel. He has been with Intel for 19+ years and played leadership roles in the convergence of several SoC. His expertise is in floorplan tech readiness, Backend methodologies, physical Integration / verification, die disaggregation using advance package technologies (Foveros, EMIB, Co-EMIB, Foveros-Direct, OSAT) development for Client, Server, IoTG, Networking products. He holds MS from BITS Pillani, India.
2.2.1 Building Energy Efficiency into Wireless IoT Semiconductor Devices
Speaker
Venkatesh Narasimhan, Sr. Director of Engineering, Silicon Labs
Joseph Kolapudi, Associate Engineering Mgr, Silicon Labs
Abstract
Almost all IoT devices or nodes carry out sensing or controlling, computing and communication, and a common requirement in these devices is an extended battery life. There has been a tremendous amount of advancement at the semiconductor device level in meeting these requirements and enabling the spread of IoT into all application areas. This tutorial covers the methods by which semiconductor designs have seen fundamental advancement at multiple levels in this area. We cover the techniques used at the device level to reduce dynamic and leakage power consumption, use of a multitude of techniques to isolate and regulate power in internal processing elements at low granularity and enabling a combination of software and hardware to achieve unprecedented efficiencies. We also cover higher level techniques that include hardware-software partitioning, selection of wireless receiver algorithms for energy efficiency, innovative approaches to reusing computational blocks, dynamic performance scaling, and the smart use of protocol supported sleep states for achieving a very low power wireless end node ASIC design without sacrificing performance. We show how battery life enhancement is a joint endeavour involving semiconductor device construction and control, the simultaneous use of multiple architecture level techniques, and a seamless approach to wireless design involving algorithms, hardware realizations and software control.
Speaker Bio
Venkatesh Narasimhan
N. Venkatesh is Senior Director, Engineering at Silicon Labs, Hyderabad coming in through its acquisition of Redpine Signals in March, 2020. He has over 35 years of engineering and management experience in wireless system design, IoT solutions, and semiconductor design. Prior to Redpine, Venkatesh was General Manager at Paxonet Communications, creating semiconductor solutions in optical networking and telecom. He started his career at Hindustan Aeronautics, designing advanced communication systems for airborne applications. He is an active IEEE volunteer and was the Chair of IEEE Hyderabad Section in 2019. He is a Charter Member and on the Board of TiE Hyderabad and mentors’ start-ups and aspiring entrepreneurs. Venkatesh holds a Masters Degree in Electrical Engineering from the Indian Institute of Technology, Madras, India. He holds 22 US patents and is a Fellow of the Indian National Academy of Engineering.
Joseph Kolapudi
Joseph Kolapudi is Associate Engineering Manager at Silicon Labs, Hyderabad, coming in through its acquisition of Redpine Signals. Joseph has over eight years of experience in Applications Engineering, enabling customers to build IoT solutions using the company’s Wi-Fi and BT chipsets and modules. He areas of expertise include developing IoT applications to showcase the connectivity and energy efficiency of the chipsets, interfacing the Wi-Fi chips to a multitude of external MCUs, and Wi-Fi 6 for IoT. He has helped create the company’s offering for Matter over Wi-Fi, Matter being the new IoT standard developed by the Connectivity Standards Alliance. Joseph has also been responsible for developing and delivering training for the company’s world-wide Field Application Engineers.
2.2.2 New era of Automotive Mobility
Speaker
- Kostas Doris, Fellow, NXP Semiconductors and part time Professor at Technical University of Eindhoven
- Preet Yadav, R&D SOC Technical Program Manager, NXP Semiconductors, India
Abstract
Part 1: Shift of Automotive from Mechanical to Electrical, evolution of next generation automotive architectures.
With the rapid advancement in the technology sphere, we are surrounded by multifold autonomous gadgets all the times. One of such major advancement is happening in mobility domain, where autonomous intelligence is at the core of the mobility. In the first part of the tutorial, we will discuss the shift from traditional mobility to smart mobility. We will focus on ever growing electronics content in automotive resulting into mega trends driving growth of autonomy, electrification and connectivity, on top of it how to secure this electrification. We will discuss the paradigm shift in the way we define architect of automotive. The major shift towards domain-based architectures which leverage processing power coupled with need to simplify vehicle networking. Finally concluding with the safety aspect of automotive.
Part 2 : Autonomous revolution focusing on Mm-wave CMOS Automotive Radar
Mm-wave automotive radar is essential sensor technology for full drive automation and evolves steadily in the 76-81GHz band. Mm-wave CMOS in particular is becoming nowadays the mainstream technology platform for high performance car radar sensors in all application segments. The combination of highly integrated RFCMOS transceivers having ever increasing levels of performance with automotive grade nano-meter scale microprocessors enables radar resolution boost in range, velocity and angle, enhanced sensing robustness and large and cost-effective sensor diversity from high performance imaging radars to corner radars. In the second part of the tutorial, we will cover mm-wave automotive radar from basic principles of ranging and detection of angle of arrival to waveform choices for MIMO, circuit requirements and RFCMOS architectures. Examples of high-performance automotive transceivers will be shown and the emerging landscape to frequencies beyond 100GHz will be sketched.
Tutorial Plan
- Shift of Automotive from Mechanical to Electrical: [90 min]
- Autonomous revolution and focusing on Mm-wave CMOS Automotive Radar: [90 min]
Speakers Bio
Kostas Doris
Kostas Doris is Fellow at NXP Semiconductors and part time Professor at Technical University of Eindhoven. Kostas is the (co-) author of several papers, patents, and books in the field of data converters and mm-wave radar. His is currently leading RFCMOS automotive radar transceiver innovation activities in NXP Semiconductors. Kostas served IEEE as Associate Editor for the IEEE Transactions of Circuits and Systems, and as Technical Program Committee and Regional EU Chair for the International Solid State Circuits Conference.
Yadav Preet
Yadav Preet is R&D SOC Technical Program Manager for Automotive Group at NXP Semiconductors. Prior to re-joining NXP in his second stint, he was working with Wipro as Analog Practice Head, Distinguished Member of Technical Staff (DMTS) – Wipro Senior Member, leading Analog & Mixed Signal Practice globally in VLSI Technology Group. He has two decades of enriched Research & Development experience in the diversified Semiconductor industry.
He is IETE Fellow and Senior Member of IEEE. He is Associate Editor of IEEE Sensors Alert. He is Chairman of IEEE Circuit & Systems Society (CASS) Delhi Chapter and member of Global IEEE CASS – VLSI Systems & Applications Technical Committee (VSATC).
2.3.1 Functional Verification of Multichip Reference Design compute subsystem for Hyperscalar SoCs
Speakers
- Alok Sharma –Principal Engineer, Cambridge, ARM
- Vikash Chandra – Director Engineering, Bangalore, ARM
- Arulvasan Muniselvam – Staff Engineer, Bangalore, ARM
Abstract
Designing subsystems for multichip Hyperscalar SoC offer faster time to market by offering RTL for a large set of advanced and complex functionalities. However, functional verification of such a complex subsystem offers significant challenges. In this tutorial, we discuss the challenges associated in functional verification for such a subsystem for single chip and multichip configurations. We discuss Emulation techniques in details that address some of the challenges faced by traditional simulation-based approaches.
We begin with introduction of ARM Neoverse N2 reference subsystem (https://developer.arm.com/documentation/102337/0000) (RD N2). We outline the approach for functional verification in a single chip configuration and discuss the associated challenges. We discuss some of potential solutions (e.g. Using FVP) in detail. This is followed by discussion on verification and associated challenges for multichip configuration space. We discuss Emulation Techniques in detail that address some of the challenges discussed.
Reference Design compute subsystem – an introduction, challenges in verification ( single chip): (Alok Sharma) [60 Mins]
- Reference Design compute subsystem – An introduction using Neoverse N2 reference subsystem as an example
- Challenges in simulation based RTL Verification (single chip)
- Fixed Virtual Platform (FVP)
Reference Design compute subsystem for Multichip usecase – Challenges in verification: (Arulvasan Muniselvam) [60 Mins]
- Multichip subsystem – An Introduction using RD-N2
- Defining the multichip verification space
- Challenges
Emulation Based Validation for Reference Design compute subsystem: (Vikash Chandra) [60 mins]
- Introduction
- Usecases for Emulation based validation/verification
- Challenges
Speakers Bio
Alok Sharma
Alok Sharma has been with ARM, Cambridge for about 7 years. Prior to joining ARM, Alok has been working with Synopsys and NXP Semiconductors in Eindhoven, The Netherlands. His area of work includes IP and subsystem verification, using simulation and formal techniques. He has worked on several generations of DDR controller IPs and compute subsystems for IoT and infrastructure domains. He is currently leading the verification activities for a compute subsystem. His interests include exploring emerging technologies in verification. Alok has done B.Tech in E.E. from IIT Delhi (1999) and Masters in E.E. from Technical University Eindhoven, The Netherlands.
Vikas Chandra
Vikas Chandra is with ARM from past 8+ Years and having overall Industry experience on 20+ years of experience in VLSI ASIC Design, Verification and Implementation. Worked on IP Unit, Sub-system and SOC level verification and validation involving simulation and emulation based platform. Extensively worked on PCIe IP verification in past and currently leading ARM system IP system level verification which also involves using PCIe and CXL as verification component . Completed his B.E in Electronics and Communication in the Year 2001 followed by PG specialization in VLSI design at CDAC Hyderabad
Arulvasan Muniselvam
Arulvasan Muniselvam has been with ARM for almost 5 Years and have an overall industry experience of 13 years. Area of work includes IP and sub system level verification using simulation platform. Prior to joining ARM, Arulvasan worked for Western Digital and Wipro. Worked on flash memory, PHY layer and Non-Coherent Interconnect IP verification in the past. Currently leading multichip verification and system level verification activities for a compute sub system. Arulvasan has a B.E degree in Electronics and Communication from PSG college of Technology and M.S in microelectronics from BITS-Pilani
2.3.2 Quantum Computing: Algorithms, Systems and Design Automation
Speakers
- Assoc Prof Anupam Chattopadhyay, Nanyang Technological University, Singapore
- Amlan Chakrabarti (CU, India)
- Susmita Sur-Kolay (ISI, Kolkata)
- Robert Wille (TUM, Germany)
- Manas Mukherjee (CQT/NUS, Singapore)
Objectives
The objectives of this tutorial are listed as following –
- Present state-of-the-art knowledge on the design and development of Quantum
computing, ranging from technologies, circuits, and open-source tools - Summarize the realistic application advances leveraging on the scalable Quantum computers
- Present latest research findings on design automation flows for complete mapping of Quantum algorithms to Quantum computers
Abstract
Following Feynman’s idea of computing based on the intricate principles of quantum mechanics the scientific community has embarked on a quest to tap into the unprecedented potential of quantum computing. The concerted effort by industry/academia has produced commercial quantum computers and algorithms that offer speed-up over classical counterparts (at least in principle).
Despite the promises and potentials, quantum computers are still in nascent stage. On the device front, the qubits are fragile and susceptible to noise and error due to decoherence. New noise tolerant qubits are being studied for this purpose. Another approach is to deploy quantum error correction (QEC) e.g., Shor code, Steane code, Surface code. Variational algorithms and hybrid classical-quantum approaches have shown promise to solve practical problems with Noisy Intermediate Scale Quantum (NISQ)-era quantum computers.
Quantum computers render promises for advancing applications in multiple domains, including cryptography, financial technologies, machine learning, drug design and quantum mechanical system simulations. These advances, when realized with a large-scale, robust Quantum computer, can leapfrog the application/system efficiency by orders of magnitude. Realizing the tremendous potential of these technologies, researchers, and industrial practitioners across a wide spectrum of disciplines are pushing individual boundaries. The goal of this tutorial is to present a sneak preview of such advances and thus, catalyse a wider array of researchers towards the common goal.
The first phase of the tutorial will discuss the growth of scalable quantum computers, their challenges, and the latest research to solve practical problems using NISQ computers. This will be followed by a glue talk connecting and establishing various advances in application scenarios for Quantum computers. The third phase of the tutorial will discuss design automation challenges of realizing complex Quantum algorithms in present-day and future Quantum computers.
Tutorial Plan
- Introduction and Organisation [15 min]
- Challenges of Scalable Quantum Computing [60 min]
- Quantum Technology Overview (Manas Mukherjee)
- Quantum Algorithms and Error Correction Overview (Susmita Sur-Kolay)
- Applications of Quantum Computers [60 min]
- Quantum Computing Applications: Cryptography (Anupam Chattopadhyay)
- Quantum Computing Applications: Optimization and Machine Learning
(Amlan Chakrabarti)
- Design Automation for Quantum Computers [60 min]
- System-level Design Flows (Amlan Chakrabarti)
- Synthesis and Compilation Flows (Anupam Chattopadhyay)
- Simulation and Testing Flows (Robert Wille)
- Q&A [15 min]
Speakers Bio
Robert Wille
Dr.-Ing. Robert Wille is a Full and Distinguished Professor at the Technical University of Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg, Austria (a technology transfer company with 100 employees). He received the Diploma and Dr.-Ing. degrees in Computer Science from the University of Bremen, Germany, in 2006 and 2009, respectively. Since then, he worked at the University of Bremen, the German Research Center for Artificial Intelligence (DFKI), the University of Applied Science of Bremen, the University of Potsdam, and the Technical University Dresden. From 2015 until 2022, he was Full Professor at the Johannes Kepler University Linz, Austria, until he moved to Munich. His research interests are in the design of circuits and systems for both conventional and emerging technologies. In these areas, he published more than 400 papers and served in editorial boards as well as various committees of numerous journals/conferences such as TCAD, ASP-DAC, DAC, DATE, and ICCAD. For his research, he was awarded, e.g., with Best Paper Awards, e.g., at TCAD and ICCAD, an ERC Consolidator Grant, a Distinguished and a Lighthouse Professor appointment, a Google Research Award, and more.
Amlan Chakrabarti
Prof. (Dr.) Amlan Chakrabarti is presently Professor and Director of A. K. Choudhury School of Information Technology (AKCSIT), University of Calcutta and additionally he is also Heading the IT and Technology Innovation Cell, Dept. of Higher Education Govt. of West Bengal. Prior to this, he completed his Post-Doctoral research at Princeton University after completing his Ph.D. from the University of Calcutta in association with ISI, Kolkata. He has almost 20 years of experience in Engineering Education and Research. He is the Fellow of the West Bengal Academy of Science and Technology and the recipient of prestigious DST BOYSCAST fellowship award in Engineering Science (2011), Indian National Science Academy (INSA) Visiting Faculty Fellowship (2014), JSPS Invitation Research Award (2016) from Japan, Erasmus Mundus Leaders Award from European Union (2017), Hamied Visiting Professorship from University of Cambridge, UK (2018), Siksha Ratna Award by Dept. of Higher Education Govt. of West Bengal (2018), IBM Quantum Researchers Program Access Award 2021. He has also served in various capacities in various higher education organizations both at national and international levels. He has received multiple project grants in the areas of Security in Cyber-physical Systems, IoT, Embedded System Design, VLSI Design, Quantum Computing, Computer Vision and Data Science from various national and international agencies (DST, DRDO, MietY, UGC, DAE, Ministry of Social Empowerment, WB-DST, Intel India, TCS etc.). He has contributed immensely in the development of intelligent algorithms and systems to support real-time applications, cybersecurity, quantum computing, healthcare, environment and water quality etc. He was the Principal Investigator of the Centre of Excellence in Systems Biology and Biomedical Engineering, University of Calcutta funded by MHRD under TEQIP-III funding during 2013-2017. Till date he has graduated 20 Ph.D. students. He has published around 200+ research papers in referred journals and conferences and 5 patents. He is a Sr. Member of IEEE and ACM, IEEE Computer Society Distinguished Visitor (2020-2022), Distinguished Speaker of ACM (2017-2020), Vice-Chair of IEEE CEDA India Chapter, Vice President of Society for Data Science and Life Member of CSI India. He is the Series Editor of Springer Transactions on Computer Systems and Networks and Springer Book Series on Waterinformatics, Associate Editor of Elsevier Journal of Computers and Electrical Engineering and Guest Editor of Springer Journal of Applied Sciences. His areas of interest are Machine Learning, Computer Vision, Cyber-physical Systems, Quantum Computing and VLSI CAD.
Susmita Sur-Kolay
Dr. Susmita Sur-Kolay received the B.Tech.(Hons.) degree in Electronics and Electrical Communications Engineering from Indian Institute of Technology Kharagpur and the Ph.D. degree in Computer Science and Engineering from Jadavpur University India. She has been a faculty member, presently Senior Professor in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata, India since 1999. During the period 1993-99, she was a Reader in the Department of Computer Science and Engineering of Jadavpur University. Prior to that, she was a post-doctoral fellow at University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also on sabbatical at Princeton University, Intel Corp., USA and University of Bremen. Her research contributions are in the areas of algorithms for design automation in emerging computing technologies, synthesis of quantum circuits, and graph algorithms. She has co-authored several technical papers in leading international journals and refereed conference proceedings, and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She was the General Co-Chair of the 29th (2016), Technical Program Co-Chair of the 18th (2005) International Conference on VLSI Design, ISVLSI 2011, 11th Symposium on VLSI Design and Test (2007), and has served on the program committees of several international conferences. She has served on the editorial board of the IET Computers and Digital Techniques, IEEE Transactions on VLSI Systems and ACM Transactions on Embedded Computing Systems. She was a Distinguished Visitor of IEEE Computer Society (India), a Senior Member of IEEE, Fellow of Indian National Academy of Engineering, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude 1980) and Distinguished Alumnus Award (2020) of IIT Kharagpur, IBM Faculty Award (2009), Women in Technology Leadership Award (2022) from the VLSI Society of India.
Manas Mukherjee
Dr. Manas Mukherjee, a Principal Investigator at the Centre for Quantum Technologies and an Associate Professor at the Physics Department, National University of Singapore, is an expert in experimental quantum technology, leading world-class research group focused on Ion Trap based quantum devices. Over the years he has contributed towards the development of different types of ion trap technologies starting from his PhD on Penning traps from the University of Heidelberg, Germany in 2004. He was a Lise Meitner Research Fellow at the University of Innsbruck, Austria in Professor Rainer Blatt’s group leading the foundational work of single photon and entangled photon generation from a single ion as well as ion-photon entanglement.
Anupam Chattopadhyay
Dr.-Ing. Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India, MSc. from ALaRI, Switzerland, and Ph.D. from RWTH Aachen in 2000, 2002, and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September 2014, Anupam was appointed as an Assistant Professor in SCSE, NTU, where he got promoted to Associate Professor with Tenure from August 2019. In the past, he held visiting positions at Politecnico di Torino, Italy; EPFL, Switzerland; Technion, Israel, and Indian Statistical Institute, Kolkata. His research interests are in Application-specific architecture, Electronic Design Automation, and Security. Anupam is an Associate Editor of IEEE Embedded Systems Letters and series editor of Springer Book Series on Computer Architecture and Design Methodologies. He received Borcher’s plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008, nomination for the best IP award in the ACM/IEEE DATE Conference 2016 and nomination for the best paper award in the International Conference on VLSI Design 2018 and 2020. He is a fellow of Intercontinental Academia and a senior member of IEEE and ACM.
