Call for Papers
Please make your submissions here:
Please note:
All papers must be in PDF format only, with savable text.
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- Each paper must be no more than 6 pages (including the abstract, figures, tables, and references), double-columned in IEEE Format (Highlighted Text Hyperlinked to https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/Conference-template-A4.doc)
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- Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person
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- Submissions not adhering to these rules, or determined to be previously published or simultaneously submitted to another conference, or journal, will be summarily rejected.
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- IMPORTANT: Final camera-ready versions must be identical to the submitted papers with the following exceptions; inclusion of author names/affiliation, correction of identified errors, addressing reviewer-demanded changes. No other modifications of any kind are allowed including modification of title, change of the author list, reformatting, restyling, rephrasing, removing figures/results/text, etc.
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- The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules.
Schedule Call For Papers
Deadline: July 7, 2019 (Sunday)
Please note: Abstract Submissions Closed
Deadline: July 15, 2019 (Monday)
Please note: (Regular) Full Paper Submissions Closed
Deadline: September 15, 2019 (Sunday)
Deadline: September 29, 2019 (Sunday)
Deadline: August 20, 2019 (Tuesday)
Please note: Tutorial Submissions Closed
Deadline: September 15, 2019 (Sunday)
Deadline: November 3, 2019 (Sunday)
Deadline: October 15, 2019 (Tuesday)
Please note: Submissions Closed!
Deadline: November 26, 2019 (Tuesday)
Updated Dates!
Deadline: December 12, 2019 (Thursday)
Updated Dates!
Topics Call For Papers
Intelligent System Design
Embedded Systems Design:
Internet of Things (IoT),ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verification, Reconfigurable Computing, Embedded Multicores SOC and Systems,Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip
Machine Learning:
Neuromorphic Computing, On Chip Learning
System Level Algorithms and Architectures:
Platform Architectures, Chip Partitioning, Power Management, Board Level Design, Packaging, Signal Integrity, Power/Thermal Trade Off
High Performance Computing:
Server Processor Architecture, Compute Efciency, Benchmark Enhancement, Edge Computing, Cloud Computing, Distributed Architecture, Heterogeneous Compute
Efficient Connectivity:
Ethernet, Networking Algorithms, 5G, Communication Standards, LTE, Switching
Security: Security Protocols
HW Security Design, SW Security, Architectures, Algorithms
Efficient Component Design
Digital Design:
Logic and Physical synthesis, Place & Route, Clock Tree Synthesis,
Physical Verification, Static/Dynamic Timing, Signal integrity, xOCV, DFM/DFY,
Physical Design for DebugAnalog Design:
Analog Mixed Signal IP, High-Speed Interfaces, Various RAM design, IO Buffer,PLL/DLL Design, Standard Cell Design
FPGA:
FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping
Power/Energy Efficiency:
Digital/Analog Power Optimization Techniques, Power Architectures, Power/Performance Trade Off, Power Delivery Network, Power Switch, Power/Thermal Balance
Verification and Test:
Post Silicon Validation, Design for Test (DFT), Product Level Test, Design Verification Techniques, Mixed Signal Verification, Fault Tolerance, DPPM Betterment, Formal Verification, Emulation
Power Management and RF:
Optimization, Regulator Design, On Chip Regulator, RF Circuits, Effective Spectrum Utilization, New Transceiver Design in 5G Era, RF Certification, LDO Design, SMPS Design
Electronic Design Automation:
Simulation Tools for Design Verification, SPICE Simulation,Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations
Emerging Technologies:
Emerging Memory Technologies, 3D Integration, Nano-CMOS Technologies, MEMS, CMOS Sensors, CAD/EDA Methodologies for Nanotechnology, Nano-Electronics and NanoCircuits, Nano-Sensors, MEMS Applications, Nano-Assemblies and Devices, NonClassical CMOS; Post-CMOS Devices; Biomedical Circuits, Carbon Nano-Tubes Based Computing
New Age Nano-Electronics and Tools/Flows/Methodologies
Electronic Design Automation:
ML Based EDA, Simulation Tools for Design Verification, SPICE Simulation, Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verification Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations, Transistor Level Tools, EDA on Cloud
Design in New Age Nano-Electronics:
Emerging Logic and Memory Technologies, Device Nanoelectronics, 2.5D and 3D TSV, 3D Integration, Interaction with Design for Manufacturing, Reliability and Test, Device Nanoelectronics, Silicon Technology Advancements, FinFET, Beyond FinFET, Transistor Level Performance Improvements, Device Microelectronics, Beyond Silicon, PVT Optimization, Design Optimization Corners, Yield Improvement, Post Tapeout Methodology