Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional “von-Neumann” architectures are several orders of magnitude more area and power expensive than the biological brain. Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of ‘data deluge’ and emergent data-centric applications. Exploring the new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations of the brain leading to a better match between the hardware substrate and the model of computation. In this presentation, we will discuss our work on spintronic device structures consisting of single-domain/domain-wall motion based devices for mimicking neuronal and synaptic units. Implementation of different neural operations with varying degrees of bio-fidelity (from “non-spiking” to “spiking” networks) and implementation of on-chip learning mechanisms (Spike-Timing Dependent Plasticity) will be discussed. Additionally, we also propose probabilistic neural and synaptic computing platforms that can leverage the underlying stochastic device physics of spin-devices due to thermal noise. System-level simulations indicate ~100x improvement in energy consumption for such spintronic implementations over a corresponding CMOS implementation across different computing workloads. Complementary to the above device efforts, we have explored different learning algorithms including stochastic learning with one-bit synapses that greatly reduces the storage/bandwidth requirement while maintaining competitive accuracy, saliency-based attention techniques that scales the computational effort of deep networks for energy-efficiency and adaptive online learning that efficiently utilizes the limited memory and resource constraints to learn new information without catastrophically forgetting already learnt data.

Priyadarshini Panda received her BE and MSc degrees from BITS Pilani, Pilani, and her PhD in electrical and computer engineering from Purdue University. She joined the electrical engineering department of Yale University in August, 2019, as an Assistant Professor. Priya’s research interests lie in Neuromorphic Computing: spanning energy-efficient design methodologies for deep learning networks, novel supervised/unsupervised learning algorithms for spiking neural networks and developing neural architectures for new computing scenarios (such as lifelong learning, generative models, stochastic networks, adversarial attacks etc.).

Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics. Kaushik Roy has supervised 85 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Human health is undergoing transformative changes with precision and personalized medicine that is hinged on measurements of highly sensitive, and specific disease biomarkers. New health diagnostics and treatment are expected to emerge through innovations in technology that has the ability to allow precision monitoring (and manipulation) of a multitude of bio-molecular signatures in ultra-miniaturized platforms, that can potentially be integrated with closed-loop autonomous treatments (such as wound healing). The applications range for this new class of biosensors span from point of care diagnostics to drug screening and discovery, and silicon IC-based heterogeneous platforms can play an enabling role. The translation is not straightforward by any means; biological measurements dominantly rely on fluorescence-based assays detectable in complex optical set ups. In this talk, I will highlight our approaches to enabling fully optics-free, millimeter-scale, multiplexed nano-optical sensors in silicon with protein measurement sensitivities comparable to commercial readers. Integrated with low-power wireless interfaces, such sensors can serve as pathways towards quasi-real time sensing in an in-vivo environment. I will also highlight some approaches towards cell-based assays to study drug effects and antibiotic resistance development.

Kaushik Sengupta received the B.Tech. and M.Tech. degrees in electronics and electrical communication engineering from the Indian Institute of Technology (IIT), Kharagpur, India, both in 2007, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 2008 and 2012, respectively. In February 2013, he joined the faculty of the Department of Electrical Engineering, Princeton University, Princeton, NJ, USA and is currently an Associate Professor in the department. His research interests are in the areas of high-frequency integrated circuits (ICs), electromagnetics, optics for various applications in sensing, imaging, and high-speed communication.

Kaushik Sengupta received the Bell Labs Prize (2017), Young Investigator Program (YIP) Award from the Office of Naval Research in 2017, the DARPA Young Faculty Award (2018) E. Lawrence Keys, Jr./Emerson Electric Co. Junior Faculty Award, `Excellence in Teaching Award’ from the School of Engineering at Princeton University in 2018 nominated by the Undergraduate and Graduate Student Council. He serves on the Technical Program Committee of the IEEE ESSCIRC, IEEE CICC, IEEE International Conference on Communications, GlobeComm and on the He is a member of the MTT-4 Committee on Terahertz technology. He has served as the Guest Editor of IEEE Journal of Solid-State Circuits, co-recipient of the inaugural IIT Kharagpur Young Alumni Achievement Award, and the 2015 IEEE MTT-S Microwave Prize.

Semiconductor advances have given us the ability to build ever more powerful electronics-based systems to interact in a greatly enhanced manner with the surrounding physical world. We certainly benefit plenty from the convenience of smart gadgets and machinery. Yet ensuring the reliability and safety of such vastly complex systems is also becoming much more challenging. Meeting the challenge implies significant changes to the way we design and test components that are hierarchically integrated into sub-systems and systems-of-systems. This talk will focus on the shift that’s underway to bring system awareness to the testing of individual components. In particular, deeper test data collection, sharing and correlation across the supply chain become essential for system failure diagnosis and health monitoring. New design and test methods to enable the system-oriented shift are highlighted. The aim is to stimulate new ideas and direction in reliability research as upcoming 5G/IoT/AI applications start to proliferate and penetrate our daily lives.

Harry Chen is currently IC Testing Scientist at MediaTek. Besides research in advanced testing topics such as defect modeling and end-to-end test data analytics, he helps promote quality-related concepts throughout the company and with key suppliers and customers. Harry actively participates in test-related conferences such as ITC, ATS, ETS, VTS, and VLSI-DAT by serving on program committees, publishing papers, and giving talks. Harry is a core member of SEMI Taiwan Testing Committee. He also leads the System-Level Test focus group in the international Heterogeneous Integration Roadmap collaborative effort. Prior to MediaTek, Harry held technical positions at Analog Devices and Cadence Design Systems. He obtained EE degrees from MIT and Stanford University.

In recent years, machine learning with deep neural networks (DNNs) has been widely deployed in diverse application domains. However, the growing complexity of DNN models, the slowdown of technology scaling, and the proliferation of edge devices are driving a demand for higher DNN performance and energy efficiency. Machine learning applications have shifted from general-purpose processors to dedicated hardware accelerators in both academic and commercial settings. In line with this trend, there has been an active body of research on both algorithms and hardware architectures for neural network specialization.

This talk presents our recent investigation into dynamic DNN optimization and low-precision quantization, using a co-design approach featuring contributions to both algorithms and hardware accelerators. First, we review static network pruning techniques and show a fundamental link between group convolutions and circulant matrices — two previously disparate lines of research in DNN compression. Then we discuss channel gating, a dynamic, fine-grained, and trainable technique for DNN acceleration. Unlike static approaches, channel gating exploits input-dependent dynamic sparsity at run time. This results in a significant reduction in compute cost with a minimal impact on accuracy. Finally, we show that similar dynamic gating approach also applies to quantization.

Zhiru Zhang is an Associate Professor in the School of ECE at Cornell University. His current research investigates new algorithms, design methodologies, and automation tools for heterogeneous computing. His research has been recognized with a Google Faculty Research Award (2018), the DAC Under-40 Innovators Award (2018), the Rising Professional Achievement Award from the UCLA Henry Samueli School of Engineering and Applied Science (2018), a DARPA Young Faculty Award (2015), and the IEEE CEDA Ernest S. Kuh Early Career Award (2015), an NSF CAREER Award (2015), the Ross Freeman Award for Technical Innovation from Xilinx (2012), and multiple best paper awards and nominations. Prior to joining Cornell, he was a co-founder of AutoESL, a high-level synthesis start-up later acquired by Xilinx.

In this talk, we address the problem of achieving “secure and resilient autonomy” in a cloud-backed distributed edge-AI environment. We call the latter paradigm “swarm-AI”, with principles drawn from bio-inspired swarm intelligence. In more detail, the problem posed is as follows: Given a swarm of heterogeneous AI engines engaged in distributed inference and in-field learning (with on-demand help from the back-end cloud), how to build in resilience and security features in order to minimize the probability of in-field failures or security breaches? A particular use case we focus on in this talk is that of smart vehicular swarms, i.e. autonomous cars, drones, etc. We examine key components of a reference application that represents the world of future wireless-communicating self-driving cars, and consider how to make such an application (and supporting system architecture) resilient to failures and malicious attacks. In particular, we dwell on the edge embedded SoC architecture and design. We point out the challenges in making such systems reliable and secure, while meeting targeted performance and energy efficiency metrics. We will present our current solution strategy and initial simulation/emulation-based results.

Pradip Bose is a Distinguished Research Staff Member and Manager of the Efficient and Resilient Systems Department at IBM T. J. Watson Research Center, USA. He holds a B.Tech. (Hons.) degree from Indian Institute of Technology, Kharagpur, and later, M.S. and Ph.D degrees from the University of Illinois at Urbana-Champaign. His current research interests are in the area of energy efficiency and resilience of AI-centric systems. He is a member of the IBM Academy of Technology and a holds the title of IBM Master Inventor. He is a Fellow of the IEEE.

Over the last four decades, microprocessor research has focused on improving performance. Various micro architectural features such as cache memories, branch prediction, superscalar, speculative and out-of-order execution, were developed to facilitate this. Side-by-side, features such as multiprogramming, multicore and hardware multithreading were incorporated to increase throughput. These features allowed multiple users to simultaneously share a processor. To isolate one user’s program from another, rudimentary security schemes such as protection rings and page table access controls bits were used. Very soon it was realized that these security schemes were insufficient. Vulnerabilities in software permitted user space programs to gain privileged access. Shared hardware became a source of information leaks that could undermine the isolation provided. The very features in the processor that were incorporated to boost performance and throughput have now become a security liability.

Hardening microprocessors for security require rethinking of processor design, where security is considered as a primary design criteria along with performance, energy, and area.  This is quite a challenge because incorporating security often comes with significant overheads. Tradeoffs would need to be made to achieve sufficient security with acceptable overheads in the other design parameters. Furthermore, security threats can arise across the computing stack — from hardware, micro-architecture, to system and application software. One solution will not fix all threats; each threat would need to be handled separately. In this talk, we will discuss some of our recent and ongoing research in developing secure microprocessors. We will discuss Hardware enabled memory protection schemes and the design of power attack protected microprocessors; micro-compartments, and support for functional programming languages that can considerably reduce software vulnerabilities.

Chester Rebeiro is an Assistant Professor at the Indian Institute of Technology, Madras. Prior to this he was a postdoctoral researcher at Columbia University. He has a Ph.D. from IIT Kharagpur in the area of hardware security. Before joining IIT Kharagpur, he worked as a Member Technical Staff at CDAC, Bangalore. His area of interests include security aspects in the operating system, architecture, and VLSI. He is particularly interested in applying learning algorithms and formal methods to analyze the security of systems.

With the increasing amount of functionality within an SOC, disaggregated SOC construction technologies such as 2.5D or 3D die integration within a package are becoming the primary enablers to integrate functionality that could exceed reticule limit. Additionally, disaggregated construction allows different dice to be on different process nodes, giving flexibility to SOC developers to modulate the cost and performance based on HW aspects that really need support from expensive and newer process nodes. Also, it eliminates the need to re-harden legacy IPs on each new process node. However, constructing SOCs through disaggregation requires solving a new set of technical problems around logic partitioning between the dice, synchronous vs. asynchronous die-to-die interconnections, analyzing mix of dice from different process nodes, die mirroring vs. rotation for design simplification, debugging and testing the dice separately and together, etc. In this talk, I will provide a few examples of how these problems manifest in the real world and discuss opportunities where tools/automation capabilities can greatly help to overcome these challenges and succeed with this new development model.

Ashok Jagannathan is an SOC architect in the Graphics SOC team at Intel, Bangalore. He is responsible for the micro-architecture definition of the first set of data-center GPU SOCs at Intel. He joined Intel, Bangalore in 2005 and has worked there ever since on the architecture and performance analysis of multiple processors covering client, server, HPC, and GPU segments. He has a Ph.D. in Computer Science from UCLA.

We introduce the cache bandwidth partitioning problem, which appears in shared last level caches that need to arbitrate to determine the order in which they serve requests they receive from different processor cores in a multicore system-on-chip. While cache space partitioning has been studied extensively earlier, the cache bandwidth partitioning problem is a new formulation. We first study the impact of this phenomenon using simulators and real machines, and determine architectural parameters affecting cache contention. The REAL policy is an algorithm that arbitrates among cache access requests from different cores by dynamically assigning a priority to the cores contending at the cache, and through this, performing a bandwidth partitioning of the cache that results in significant system performance improvements.

Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University.

His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal.

Prof. Panda has served on the the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters, IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and International Journal of Parallel Programming (IJPP), and as Technical Program co-Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.

Multi-robot systems, working collaboratively to accomplish complex missions provide a very optimized and cost effective solution for multiple applications because of the inherent parallelism and redundancy compared to deploying single robot systems. With the scaling of sensors in size and cost, it is  possible to build very small and cost effective solutions for applications like search & Rescue, inspection, precision agriculture etc  where the compute itself becomes a bottleneck because of the complex algorithms that need to be implemented. In this talk I will present a mm scale low power  Soc research prototype in 22nm CMOS that is integrated on a cm scale minibot platform along with various sensors, battery and low power wireless communication to demonstrate a distributed autonomous multi-robot system. The functions integrated on the SoC include sensor data fusion, real time processing, object detection, collision avoidance and pathplanning, motion control and collaborative decision making. Each minibot platform integrates: (i) camera, LIDAR & audio sensors for real-time perception & navigation; (ii) low power  SoC (iii) low power ultra-wideband (UWB) radio for anchorless dynamic ranging & inter-robot information exchange; (iv)long range radio (LoRa) for robot-to-base-station critical message delivery; (v) battery & PMIC for platform power delivery & management; (vi) 64MB pseudo-SRAM (PSRAM) &1GB flash memory; and (vii) actuators for crawling & jumping motions.

Anuradha Srinivasan is currently senior director of Silicon and Systems Prototyping labs at Intel Labs working out of Portland Oregon. She has extensive experience in leading teams in the development of low power SoCs for edge applications. She has been with Intel for 17years, has a bachelor’s degree in Electronics and Communication and has 1 patent pending.

The high-performance and energy-efficient encryption engines have emerged as a key component for modern System-On-Chips (SoCs) in various platforms including servers, desktops, mobile, and IoT edge devices. A key bottleneck to secure operation of encryption engines is leakage of information through side-channels. For example, an adversary can extract the secret key by performing statistical analysis on measured power and electromagnetic (EM) emission signatures generated by the hardware during encryption. Countermeasures to such side-channel attacks often come at high power, area, or performance overhead. Therefore, design of side-channel secure encryption engines is a critical challenge for high-performance and/or power-/energy efficient operations. This talk will discuss that although low-power need imposes critical challenge for side-channel security, but circuit techniques traditionally developed for power management also present new opportunities for side-channel resistance. As a case-study, we show the feasibility of using integrated voltage regulator and dynamic voltage frequency scaling normally used for efficient power management, for increasing side-channel resistance of AES engines. The hardware measurement results from test-chip are presented to demonstrate the impact of power management circuits on side-channel security.

Saibal Mukhopadhyay he is a Joseph M. Pettit Professor at the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He holds a PhD degree from electrical and computer engineering, Purdue University. His current research interests include neuromorphic computing, power and thermal management, and hardware security. Saibal Mukhopadhyay received the Office of Naval Research Young Investigator Award in 2012, the National Science Foundation CAREER Award in 2011, the IBM Faculty Awards in 2009 and 2010, and the SRC Technical Excellence Award in 2005. He has received many Best Paper Awards in IEEE Transactions and IEEE conferences. He has authored or co-authored over 250 papers in refereed journals and conferences and has been awarded six (6) U.S. patents.

Very Large Scale Integration (VLSI) methodology and manufacturing process has grown rapidly in the last few decades enabling us to design and encapsulate billions of transistors in single mammoth chips. Design For Excellence (DFX) such as – Design for Functional Safety (DFS), Design For Testability (DFT), and Design For Manufacturing (DFM) – encompass several aspects of VLSI methodology and manufacturing process towards realizing these System-on-Chips (SoCs)

Autonomous Vehicles (AV) are beginning to surface up in the streets of USA, Europe, & Asia. These self-driving vehicles are equipped with a variety of sensors to perceive the surroundings, obstructions, traffic signs, and coordinates. Real-time processing and decision-making for these AVs are implemented by powerful Graphic Processing Units (GPUs) based System-on-Chips (SoCs). VLSI DFX plays a very important role in realizing these GPU based SoCs from design concept-to-tapeout.

In this talk, we will introduce design features of AV vehicles, and the GPU based SoCs that forms the cockpit for these AV vehicles. We will delve into VLSI methodology aspects into designing these GPUs and SoCs. In particular, we will cover a few DFX aspects such as DFS, DFT, and DFM. We will also introduce the International Standards Organization (ISO) mandate for Functional Safety in AVs and the needs for its compliance.

We introduce the cache bandwidth partitioning problem, which appears in shared last level caches that need to arbitrate to determine the order in which they serve requests they receive from different processor cores in a multicore system-on-chip. While cache space partitioning has been studied extensively earlier, the cache bandwidth partitioning problem is a new formulation. We first study the impact of this phenomenon using simulators and real machines, and determine architectural parameters affecting cache contention. The REAL policy is an algorithm that arbitrates among cache access requests from different cores by dynamically assigning a priority to the cores contending at the cache, and through this, performing a bandwidth partitioning of the cache that results in significant system performance improvements.

Rajagopalan (Gopal) Srinivasan currently manages functional safety engineering aspects for Graphics Processing Units (GPUs) at Nvidia Corporation in Santa Clara, USA. Prior to the current assignment, he led the Design for Testability (DFT) aspects for all Nvidia Central Processing Units (CPUs) and their associated Tegra System-on-Chips (SoCs). Gopal has more than 25 years of extensive technical design and management experience having worked for various organizations – Intel Corporation in Folsom, California (CA) & Morganville, New Jersey (NJ), Lucent Bell Labs (now Nokia Labs) at Murray Hill & Princeton in NJ, Stanford University Network (SUN) Microsystems (now Oracle Corp.) at Menlo Park, CA, Texas Instruments (TI), Bangalore. Gopal received his B. Tech in Electronics from the Indian Institute of Technology, Madras, M.E. in Computer Science & Communications from the Indian Institute of Science, Bangalore, M.S. & Ph.D. in Computer Engineering from the University of Southern California, Los Angeles. Gopal has published several technical papers and articles in IEEE/ACM Conferences and Transactions. He has been in Technical Program Committees for various International Conferences and has represented Nvidia in several Technical Panels.

The dictionary definition of “sensing” is expanding rapidly. “Sensing” technology was founded on the basis of “sensor and instrumentation” and went beyond a domain, where it’s becoming a non-separable part of a much wider set of domains. In the context of “sensing technology for individuals” there are many factors which affect the choice of application, development path and product customization. Starting from signals, as a part of the wide domain of sensing, conditioning the signals from sensing elements, digitization and transfer to the available devices with controlled energy consumption and power autonomy play key roles. The need for more modular and affordable IPs,
which can be seamlessly integrated, is felt for developing indigenous products in this impactful area. This talk will focus on the analog, mixed-signal and RF designs of the three sub-areas: signal conditioning, short range bio-telemetry and energy harvesting & power management. The examples are based on reported and in-house designs. The talk will then cover thoughts around the scope, opportunities and requirements for indigenous product development.

Maryam Shojaei Baghini received the M.S. and Ph.D. degrees in Electrical Engineering from Sharif University of Technology, Tehran, in 1991 and 1999, respectively. She worked for more than 2 years in industry on the design of analog ICs. In 2001, she joined Department of Electrical Engineering, IIT-Bombay, as a Postdoctoral Fellow, where she is currently a Professor.

Maryam Shojaei has published more than 235 peer reviewed international journal and conference papers. She is the inventor/co-inventor of 6 granted US patents, 3 granted Indian patents and 43 more filed patent applications. Her research areas span from devices and sensors to the integrated instrumentation circuits & sensor systems, energy harvesting circuits and systems, and analog/mixed-signal/RF design for emerging applications.

Maryam Shojaei has served as in the Technical Program Committee of several conferences including recently as AMS-RF track chair in International Conference on VLSI Design 2020, Organizing Chair for IEEE IMaRC 2019 and WSN track chair in IEEE Sensors Conference 2018 and 2019. She was a TPC member of IEEE-ASSC from 2009 to 2014. Maryam Shojaei is recipient/joint recipient of 12 awards, of which the recent award is the Best Paper Award in International Conference on VLSI Design 2019.

Digital computing is based on a deterministic bit with two values, 0 and 1. On the other hand, quantum computing is based on a q-bit which is a delicate superposition of 0 and 1. This talk draws attention to something in between namely, a p-bit which is a robust classical entity fluctuating between 0 and 1, and can be built with existing technology to operate at room temperature.

We have shown that these p-bits can be used as building blocks for constructing autonomous p-circuits that can accelerate many current applications like optimization, invertible logic and machine learning, while providing a bridge to the emerging field of quantum computing.

Key References:

[1] W.A. Borders et al. “Integer Factorization using Stochastic Magnetic Tunnel Junctions,” Nature 573, 390 (2019).
[2] K.Y. Camsari et al. “Scalable Emulation of Sign-Problem–Free Hamiltonians with Room- Temperature p-bits,” Physical Review Applied 12, 034061 (2019).
[3] K.Y. Camsari et al. “p-bits for probabilistic spin logic,” Appl. Phys. Reviews 6, 011305 (2019).

Kerem Y. Camsari is a post-doctoral research associate at the School of Electrical and Computer Engineering at Purdue working with the Supriyo Datta group. His PhD thesis focused on establishing the “Modular Approach to Spintronics”, bringing a wide range of physical methods such as the Non-Equilibrium Green’s Function (NEGF) method, spin diffusion (Valet-Fert) equations for transport, and LLG for magnet dynamics into a unified SPICE compatible circuit framework. His postdoctoral work has been about probabilistic computing that makes use of compact probabilistic bits (p-bit) as building blocks for p-circuits. These p-circuits have been shown to be potentially useful energy-efficient accelerators for both machine learning and quantum inspired algorithms. Kerem has co-authored more than 35 papers in refereed journals and conferences and has delivered 15 invited talks in international conferences and workshops on his work.

In the on-going era of artificial intelligence (AI) and Internet of Things (IoT), semiconductor industry has actively been developing embedded-MRAM (eMRAM) based on perpendicular magnetic tunnel junction (MTJ), aiming for a variety of applications such as embedded flash (eFlash), slow SRAM (< 50 MHz), and cache-like SRAM. To support such a broad range of products with one technology platform, it is crucial to evaluate eMRAM reliability and understand the trade-off among MTJ device performances to further optimize eMRAM reliability for targeted applications. In this talk, the status of 22nm FD-SOI eMRAM technology and the potentials of eMRAM for industrial-grade memory platform and SRAM replacement will be presented. With these potentials fulfilled, eMRAM is expected to take-off as a valuable technology differentiator add-on to various CMOS technology platforms.

Vinayak Bharat Naik has received Ph.D. degree in Physics from National University Singapore in 2011. He is currently a Senior Member of Technical Staff at GLOBALFOUNDRIES (2014 to present), Singapore leading MRAM Device team. Prior joining to GLOBALFOUNDRIES, he was working as a Scientist at Agency for Science, Technology and Research (A*STAR), Singapore (2011-2014) on conventional and voltage-controlled STT- MRAM development. He has published 45+ technical papers in international journals, and holds more than 15+ U.S. patents in the field of Non-volatile memory technologies.

The end of 60 years of Moore’s law, the stagnation of Dennard’s scaling and the need to tackle with new application domains with stringent compute and memory requirements, requires a paradigm shift in the way we design and manage the many-core processors and servers of the future. Specifically, the advent of Artificial Intelligence workloads, such as Deep Learning, has led to the need of designing more performant, energy-efficient and reliable multiprocessor Systems-on-Chip (MPSoCs), for both the embedded and high-performance computing domains. The challenge resides on improving the performance per watt while at the same time increasing the Mean Time To Failure (MTTF), thus reducing faults. To this end, proactive thermal management plays a crucial role. However, traditional control knobs such as workload allocation or DVFS, specially within the scope of heterogeneous systems equipped with accelerators for deep learning, need to consider not only performance and reliability, but also accuracy. In this area, the use of approximate computing techniques, able to trade-off performance by accuracy, has raised as a relevant solution to tackle these challenges. In this talk I will describe the work we have developed at the Embedded Systems Lab (ESL) of EPFL on the design of thermal and reliability models for MPSoCs equipped with arbitrary cooling devices, and their impact on the MTTF, as well as the management policies we have proposed that make use of approximate computing techniques.

Marina Zapater is currently a Research Associate in the Embedded Systems Laboratory (ESL) at the Swiss Federal Institute of Technology Lausanne (EPFL). She was non-tenure track Assistant Professor of ECE at Universidad Complutense de Madrid, Spain, in the academic year 2015-2016. She received her Ph.D. degree in Electronic Engineering from Universidad Politecnica de Madrid in 2015, a M.Sc. in Telecommunication Engineering degree and a M.Sc. in Electronic Engineering degree, both from the Universitat Politecnica de Catalunya, in 2010. Her research interests include proactive and reactive thermal and power optimization of complex heterogeneous systems, novel cooling techniques for 2D and 3D chips,  energy efficiency in data centers, ultra-low power architectures and embedded systems. In this area, she has co-authored over 50 publications in top-notch international conferences and journals, and has over 300 citations with an h-index of 10. She has been PI or co-PI in four projects with industrial and academic partners, she is the Scientific Coordinator of 4 European H2020 projects and has participated in more than 10 projects with industry and academic partners. She has served as TPC member for several conferences, including DATE, ISLPED, VLSI-SoC, VLSID, MCSoC. She is a member of IEEE and CEDA, and Young Professionals representative of IEEE CEDA.

This presentation provides an overview of integrated clocking technology and IPs developed in CMOS process.  We discuss four categories of clock generation IPs for applications in wireline SERDES, wireless base station local oscillators (LOs), digital timing in system-on-chip (SoC) devices, and reference or recovered clock jitter attenuation.  The evolution of clocking IPs from older CMOS technology nodes to 16nm FinFET is tracked through Figure-of-Merits aiming at improving a combination of power dissipation and clock phase noise or jitter, as well as silicon die area.

Hormoz Djahanshahi received the B.Sc. (Hons.) and M.Sc. (Hons.) degrees in Electronics Engineering from Tehran Polytechnic University, and Ph.D. degree in Electrical & Computer Engineering from the University of Windsor in Canada. In 1997-1999, he was a Post-Doctoral Fellow at the University of Toronto, where he designed high-speed CMOS and InP circuits in collaboration with Nortel Networks. From 2000 to 2018, he was with Mixed-Signal Design Group at PMC-Sierra (acquired by Microsemi in 2016), where he developed architecture and designed numerous analog IPs for high-performance multi-GHz wireline and wireless applications with a focus on clocking and PLLs. He is currently a Senior Technical Staff with Microchip Technology (formerly Microsemi and PMC-Sierra) in Vancouver, BC. He has more than 40 technical papers, 25 U.S. patents granted, and several patents pending. He has been a member of ITRS RF-AMS Workgroup in 2012-2013, and a member of standard developing bodies, including OIF and PCI-Express since 2015.

RADAR was a key technology that won the second world war for the allies. However, the frequency synthesizer from early radars, the magnetron, has now been relegated to the inside of the microwave oven. CMOS scaling and its rapid adoption in RF integrated circuits has led to billions of users of modern cellular phones, spanning multiple generations. Many of the technologies originally developed for cellular RFICs are now finding a new home in radars-on-chip for portable, low form-factor applications. While conventional pulsed radars require stable, high spectral purity oscillators, more recent FMCW and PMCW radars impose additional constraints, on parameters such as linearity. In this talk, the speaker will describe multiple generations of RADAR frequency synthesizers, and specifically discuss the challenges faced while designing them for radars-on-chip.

Gaurab Banerjee received the B.Tech. (Hons) degree from IIT Kharagpur, the M.S. degree from Auburn University and the Ph.D. degree from the University of Washington, Seattle, all in electrical engineering. In 1999, he joined Intel Corporation, Hillsboro, OR, USA, to design analog and mixed-signal integrated circuits (ICs) for the first Pentium-4 microprocessor. From 2001 to 2007, he was with Intel Labs, where he worked on CMOS-based analog, mixed-signal, and RF circuits for wireless and wireline communication systems. From 2007 to 2010, he was with Qualcomm Inc., in Austin, TX, USA, where he was involved in RFIC design for mobile broadcast video applications and the inclusion of an industry-first BIST subsystem in an RFIC product.  He joined the Department of Electrical Communication Engineering at the Indian Institute of Science in 2010, where he is currently an Associate Professor. His research interests include the design and test of analog and RFICs and systems for communication and sensor applications.

Gaurab Banerjee is a National Talent Search Scholar of India.  He has also received the Visveswaraya Faculty Fellowship from the Ministry of Electronics and Information Technology of the Government of India. Gaurab Banerjee was an Associate Editor of the IEEE Transactions on Circuits and Systems: Part-I, from 2008 to 2010. He has served as a reviewer for many IEEE journals and conferences.

In-memory computing and other memory-centric computational approaches like neuromorphic computing are generating much attention as we address the memory-wall bottleneck for emerging data-abundant computing. The need for more on-chip memory embedded near computing units can be achieved by enabling monolithic 3-D integrated circuits. Such an approach can densely incorporate memory and logic devices above conventional Silicon CMOS. However, low-thermal budget materials and processes are needed due to material stability constraints of modern metal-low-k dielectric interconnect wires. In this talk, we look at the possibilities of new materials with new in-memory computing approaches for monolithic 3D memory.  For example, we show at the material level, that defect engineering of low-thermal-budget 3-D oxides and 2-D Transition Metal Dichalcogenides enable an interesting range of nonvolatile logic and memory hybrid devices. While, we developed 2D and 3D matrix-matrix in-memory multiplication optimized for these new material systems. We show that significant gains (>10x) in energy savings, data throughput, and area efficiency with respect to conventional GPU implementations can be earned with the co-design of such systems. We show that deep convolutional neural nets (DCNN) leverages 3D memory architecture very well with a well-optimized algorithm. Going beyond the 2-terminal devices, we show that we can implement memtransistors for new Bio-inspired computing like Spiking Neural Networks. This paves the way for exciting new possibilities for new neuromorphic computing system that are based on beyond-Silicon technologies.

Aaron Thean is a Professor of Electrical and Computer Engineering and Dean of the School of Engineering at the National University of Singapore. In addition, he also holds several technical leadership responsibilities at the University; which includes Director of Applied Materials – NUS corporate research lab, HiFES research program on Hybrid Flexible Electronics, NUS’s Nanofabrication Centre, E6Nanofab. Prior to NUS, Aaron was the Vice President of Logic Technologies at IMEC. Working with Semiconductor Industry leaders like Intel, TSMC, Samsung, and Globalfoundries. He directed the research and development of next-generation semiconductor technologies and emerging nano-device architectures.  Prior to joining IMEC in 2011, he was with Qualcomm’s CDMA technologies in San Diego, California. There, he was leading the Strategic Silicon Technologies Group. Aaron and his group worked on Qualcomm’s 20nm and 16nm mobile System-On-Chip technologies.   From 2007 to 2009, Aaron was the Device Manager at IBM, where he led an eight-company process technology team to develop the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York, from research to risk production. The technology was transferred successfully to several foundry partners, the technologies became the Industry’s first foundry-compatible Gate-First High-k Metal-Gate with novel SiGe channel Low-Power bulk CMOS technologies. It successfully enabled some of today’s most successful mobile devices by Samsung and Apple.

Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors), M.Sc., and Ph.D.  degrees in Electrical Engineering. He has published over 300 technical papers and holds more than 50 US patents. Active in local and international advanced electronics communities, Aaron is an Editor of the IEEE Electron Device Letters and he serves on several Scientific Advisory Boards that include Singapore-MIT Alliance (SMART-LEES), A*Star Institute of Microelectronics (IME), Huawei Singapore Research Center, and he is Consulting CTO to IMEC CEO.