Welcome to Embedded and VLSI Design Conference 2019
– Cadence® Tensilica® Hackathon!
|
"Porting deep Neural Network for Cadence® Tensilica® AI Processor"
Winning hacks will be judged based on objective performance numbers which are output by XNNC and also subjective evaluation of approach used by participants Number of entries are limited to only 15 teams. You can form your own team of up to 3 members. Awards will be presented at the Awards Ceremony on the evening of January 8, 2019. Registration Please send your entries by email with your names, name of institution to [email protected] by December 20, 2018. Along with your entry email, include a short description about yourself and your team. Schedule Hackathon prep-up training – January 5 at 9.00AM sharp Contest time –January 5, 12noon to January 6, 12noon Venue IIT Delhi Campus Hauz Khas, New Delhi What will be provided?
1st place team cash prize of INR 65,000 2nd place team cash prize of INR 35,000 |
VLSI Design Conference started as a simple idea in 1985: to sense the level of VLSI activities in India with a focus on engineering education & research. Over the years, the conference has grown equilaterally with a VLSI community that includes the likes of Multinational Industries, Academic contributors and Government bodies around the globe. With its global footprints VLSID is recognized as a 'Sister Conference' of Design Automation Conference. This conference is sponsored by VLSI Society of India (VSI).