Embedded & VLSID Design Conference

Main Conference Technical Programme - Detailed

January 5, 2019 (Saturday) - Tutorials
Time		Ashoka	Taber	Shamsher	Mayur	IIT Delhi
8:00	9:00	Tutorial Registration
9:00	10:30	T1A: Automotive Security The Autonomous Automotive Robustness Duo: Challenges and Practice in Functional Safety and Security Session Chair: Namita Sharma Prof. Sandip Ray (University of Florida, USA) Half-day Tutorial	T1B: IoT-AI Ecosystem Designing in the Next Generation IoT-AI Ecosystem Session Chair: Prof. Sujay Deb Dr. Manish Sharma (Samsung) and Mahesh Babu A K (Samsung) Half-day Tutorial	T1C: Clock Synthesis Architecture and circuits for fractional-N clock synthesis in wireline/wireless applications Session Chair: Sneh Saurabh Prof. Saurabh Saxena (IIT Madras) and Prof. Nagendra Krishnapura (IIT Madras) Full-day Tutorial	T1F: DFT of Low Power SoCs [Hands-on Tutorial] Architecture & Methodology for DFT of Low Power SoCs Session Chair: Nitin Kishore Jais Abraham (Qualcomm) and Arvind Jain (Qualcomm)	Hackathon
10:30	11:00	Tea Break
11:00	12:30	T1A continued …	T1B continued …	T1C continued …	T1F continued …	Hackathon
12:30	1:30	Lunch Break
1:30	3:00	T1D: Logic Locking Logic Locking: Current Trends, Attacks and Future Directions Session Chair: Namita Sharma Prof. Ujjwal Guin (Auburn University, USA) and Prof. Pramod Subramanyan (IIT Kanpur) Half-day Tutorial	T1E: Analog Validation The black art of analog design and validation: where search and optimization meet Session Chair: Prof. Sujay Deb Prof. Shobha Vasudevan (University of Illinois at Urbana Champaign, USA) Half-day Tutorial	T1C continued …	T1G: FPGAs Using OpenVINO [Hands-on Tutorial] Accelerating Deep Learning Inference On FPGAs Using OpenVINO Vikas Hosoor (Intel) Session Chair: Nitin Kishore Prof. Vikas Hosoor, Sr. FAE, Programmable Solutions group, Intel Corporation	Hackathon
3:00	3:30	Tea Break
3:30	5:00	T1D continued …	T1E continued …	T1C continued …	T1G continued …	Hackathon

January 6, 2019 (Sunday) - Tutorials
Time		Ashoka	Taber	Shamsher	Mayur	IIT Delhi,/
8:00	9:00	Tutorial Registration
9:00	10:30	T2A: Memory Testing Offset in Low-Voltage Sense Amplifiers and its Implication on Memory Testing Session Chair: Farhad Merchant (RWTH Aachen University) Prof. Manoj Sachdev (University of Waterloo, Canada) Half-day Tutorial	T2B: Validation Coverage Extending the validation coverage continuum from pre-silicon to post-silicon Session Chair: Namita Sharma (Intel) Gaurav Verma (NXP), Ashish Gupta (NXP) and Nagabhushan Reddy (Intel)Half-day Tutorial	Design Contest	T2C: Vision Based Autonomous Systems Vision based Autonomous Systems Session Chair: Nalesh S (Cochin University) Prof. Chetan Arora (IIT Delhi) and Prof. Saket Anand (IIT Delhi) Half-day Tutorial	Hackathon
10:30	11:00	Tea Break
11:00	12:30	T2A continued …	T2B continued …	Design Contest	T2C continued …	Hackathon
12:30	1:30	Lunch Break
1:30	3:00	T2D: IoT Security Hardware Security of Embedded Systems and IoT Environment Prof. Susmita Sur-Kolay (ISI, Kolkata) and Prof. Debasri Saha (University of Calcutta) Half-day Tutorial	T2E: Energy and Resilience Energy-Efficient Resilience for Cognitive Systems Dr. Pradip Bose (IBM) and Prof. Subhasish Mitra (Stanford, USA) Half-day Tutorial	Design Contest	T2F: IoT for Healthcare IoT for Smarter Healthcare: From Device to Architecture, Applications and Analytics Prof. Nikil Dutt (University of California, Irvine) and Iman Azimi (University of Turku, Finland) Half-day Tutorial
3:00	3:30	Tea Break
3:30	5:00	T2D continued …	T2E continued …	Design Contest	T2F continued …

Time		January 7, 2019 (Monday)
8:00	9:00	Registration
9:00	9:45	Inauguration Ceremony at Zorawar Auditorium
9:45	10:30	Keynote at Zorawar Auditorium Title : Semiconductors for the Connected World – Safe, Secure, Smart Meindert Van Den Beld VP - Strategy Automotive Business, NXP Semiconductor
10:30	11:20	Keynote at Zorawar Auditorium Title : Computational Self-Awareness: A Paradigm for Adaptive, Resilient Cyber-Physical Systems Nikil Dutt Distinguished Professor, Departments of Computer Science, Cognitive Sciences, and EECS, University of California, Irvine
11:20	11:50	Tea/Coffee Break
		Ashoka	Taber	Shamsher	Mayur	Zorawar
11:50	13:10	Track 1A: Embedded Systems – I	Track 1B: Analog/Mixed Signal – I	Track 1C: Digital Design – I		Startup Forum - Panel Discussion: “Semiconductor Startups in India – A pipe dream"
		Session Chair: Prof. Aviral Shrivastava, Arizona State University	Session Chair: Prof. Mukul Sarkar, IIT Delhi	Session Chair: Sourav Roy, NXP

		Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples - [Best Paper Award Nominee] Sumana Ghosh, Dey Soumyajit and Pallab Dasgupta Indian Institute of Technology Kharagpur	Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination Antroy Roy Chowdhury, Nijwm Wary and Pradip Mandal Indian Institute of Technology Kharagpur	Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals - [Best Paper Award Nominee] Jinti Hazarika, Mohd Tasleem Khan and Rafi Ahamed Indian Institute of Technology Guwahati

		Write Variation Aware Non-Volatile Buffers for On-Chip Interconnects - [Best Paper Award Nominee] Khushboo Rani and Hemangee Kapoor Indian Institute of Technology Guwahati	Ultra Low Energy Reduced Switching DAC for SAR ADC -[Best Paper Award Nominee] Japesh Vohra and Vinayak Gopal Hande Indian Institute of Technology Ropar	Reducing the Overhead of Stochastic Number Generators Without Increasing Error Yudai Sakamoto and Shigeru Yamashita Ritsumeikan University

		Performance Enhancement of Caches in TCMPs using Near Vicinity Prefetcher Dipika Deb, John Jose and Maurizio Palesi Indian Institute of Technology Guwahati	A Current Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Feed-forward Compensation Abirmoya Santra and Qadeer Khan Indian Institute of Technology Madras	Low Complexity & Improved Efficiency of Encoded Data Using Peres Half Adder in BWA with Testable Feature Tripti Nirmalkar, Deepti Kanoujia and Kshitiz Varma

		EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs Somdip Dey, Enrique Zaragoza Guajardo, Amit Kumar Singh and Klaus McDonald-Maier University of Essex Karunakar Reddy Basireddy, University of Southampton Xiaohang Wang, South China University of Technology	MOS Varactor RO architectures in Near Threshold Regime using Forward Body Biasing techniques Lalit Dani, Neeraj Mishra and Anand Bulusu Indian Institute of Technology Roorkee	A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design Farhad Merchant, Institute for Communication Technologies and Embedded Systems, RWTH Aachen University Tarun Vatwani and Anupam Chattopadhyay, Nanyang Technological University Somyendu Raha and S K Nandy, Indian Institute of Science Ranjani Narayan, Morphing Machines Pvt. Ltd Rainer Leupers, RWTH Aachen University
13:10	14:10	LUNCH
14:10	14:55	Keynote at Zorawar Auditorium Title : Defining Superior User Experience in Next Gen Connected World Srini Maddali Qualcomm India
15:05	15:50	Panel Discussion at Zorawar Auditorium Topic : Autonomous Intelligence for a Safe, Secure and Smart world				Mayur
						Ph.D Forum
						Thesis-A
15:50	16:20	Tea Break
		Ashoka	Taber	Shamsher	Mayur	Zorawar
16:20	17:20	Track 2A: Security – I	Track 2B: Test and Validation – I	Track 2C: RF Design		Startup Forum Talks : “Start up to Scale up in IoT; from proof of concept to Production" Amit Gupta, CTO, Eron Energy Kuttappa Bittiananda, VP, ISG Sales, ARM-India
		Session Chair: Prof. Debdeep Mukhopadhyay, IIT Kharagpur	Session Chair: Prof. Masahiro Fujita, University of Tokyo	Session Chair: Prof. Tarun Bhattacharyya, IIT Kharagpur

		A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration - [Best Paper Award Nominee] Richa Agrawal and Ranga Vemuri University of Cincinnati Mike Borowczak, University of Wyoming	A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits - [Best Paper Award Nominee] Pradip Biswal, IIIT Bhagalour Santosh Biswas, IIT Bhilai	19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications Vipul Jain, Saurabh Kumar Gupta and Gaurab Banerjee, Indian Institute of Science Vishal Khatri, IBM INDIA Pvt. Ltd., Bangalore

		An Efficient Memory Zeroization Technique Under Side-Channel Attacks Ankush Shrivastava and Prokash Ghosh NXP India Pvt Ltd	RTL Test Generation on Multi-Core and Many-Core Architectures Aravind Krishnan Varadarajan and Michael Hsiao Virginia Tech	Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical Receivers - [Best Paper Award Nominee] Abhishek Srivastava, IIIT, Hyderabad Maryam Shojaei Baghini, Indian Institute of Technology Mumbai

		Two-Pattern Delta-IDDQ Test for Recycled IC Detection Prattay Chowdhury, Ujjwal Guin, Adit Singh and Vishwani Agrawal Auburn University	On-chip MISR compaction technique to reduce diagnostic effort and test time Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi and Kushal Kamal IIT Bombay and Global foundaries	IIP3 Improvement in Subthreshold LNAs using Modified Derivative Superposition Technique for IoT Applications Anant Rungta and Kavindra Kandpal Birla Institute of Technology and Science, Pilani

		Parallelization of brute-force attack on MD5 hash algorithm in FPGA Maruthi Gillela and Venkat Reddy Ginjala RCI, DRDO Vaclav Prenosil, Masaryk University, Brno	RSBST: A Rapid Software-based Self-test Methodology for Processor Testing VM Suryasarman and Aryabartta Sahu Indian Institute of Technology Guwahati Santosh Biswas, Indian Institute of Technology Bhilai	Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer Architecture Rohit Rothe and Rajesh Zele Indian Institute of Technology Bombay

Time		January 8, 2019 (Tuesday)
8:00	8:50	Registration
8:50	9:35	Keynote at Zorawar Auditorium Dheemanth Nagaraj Intel India Design Center Title: Computing for the Data-Centric Era
9:35	10:20	Keynote at Zorawar Auditorium Title : CONIX: Computing on Network Infrastructure for New Generation of Cyber-Physical Systems and Applications Rajesh Gupta University of California, San Diego
10:20	10:40	Tea/Coffee Break
		Taber	Shamsher	Mayur	Ashoka	Zorawar
10:40	12:00	Track 3A: Power and Energy – I Session Chair: Prof. Aryabartta Sahu, IIT Guwahati	Track 3B: CMOS Devices Session Chair: Prof. Sudeb Dasgupta, IIT Roorkee	Track 3C: Emerging Tech – I Session Chair: Prof. Rajat Kumar Pal, University of Calcutta	Industry Forum Talks	Women In Engineering (WiE) Forum Talk - The High Achievers Session Chair: Ashwini Khandekar Intel
		Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications - [Best Paper Award Nominee] Pramod Kumar Bharti, Neelam Surana and Joycee Mekie Indian Institute of Technology Gandhinagar	An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors - [Best Paper Award Nominee] Amratansh Gupta, Mohit Ganeriwala and Nihar Mohapatra Indian Institute of Technology Gandhinagar	Modelling and fabrication of mixing in low-cost passive PDMS micromixers T Pravinraj and Rajendra Patrikar Centre for VLSI and Nanotachnology, Visvesvaraya National Institute of Technology, Nagpur	10:30-10:55 am Autonomous Driving using Radar / Vision: Key Challenges Amardeep Punhani NXP 10:55 - 11:20 Intelligence leading the Artificial Intelligence Venkat Bringi Global Foundries 11:20 - 11:45 Embedded Deep Learning for Energy Constrained Systems Nitin Chawla ST Microelectronics
						10:35 - 11:00 Krishna Paul PE - Intel

		Ultra Low Power Digital Front-End for Single Lead ECG Acquisition Sanket Thakkar and Biswajit Mishra DA-IICT, Gandhinagar	Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors Manish Gupta and Abhinav Kranti Indian Institute of Technology Indore	Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation Tapalina Banerjee, Indian Statistical Institute, University of Calcutta Sudip Poddar, Indian Statistical Institute, Indian Institute of Engineering Science and Technology Sarmishtha Ghoshal, Indian Institute of Engineering Science and Technology Bhargab Bhattacharya, Indian Statistical Institute, Kolkata
						11:00 - 11:25 Prof Bhaumik
		Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power Gating Sumanta Pyne National Institute of Technology Rourkela	Delay Skew Reduction in IO Glitch Filter Kiran Gopal and Avanish K NXP India	Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips Mohammed Shayan, Sukanta Bhattacharjee and Yong-Ak Song New York University Abu Dhabi Krishnendu Chakrabarty Duke University Ramesh Karri NYU
						11:25 - 11:50 Reenee Raizada Tayal Cadence
		An Energy Efficient In-Memory Computing Machine-Learning Classifier Scheme Shixiong Jiang, Sheena Priya, Naveena Elango, James Clay and Ramalingam Sridhar University at Buffalo	Insights on anisotropic dissipative quantum transport in n-type Phosphorene MOSFET Madhuchhanda Brahma, Arnab Kabiraj and Santanu Mahapatra Indian Institute of Science Bangalore	Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits Anirban Bhattacharjee and Hafizur Rahaman Indian Institute of Engineering Science and Technology (IIEST) Shibpur Chandan Bandyopadhyay, Indian Institute of Engineering Science and Technology Robert Wille, Johannes Kepler Universität Linz Rolf Drechsler, University of Bremen
12:00	12:10	Session Break
		Taber	Shamsher	Mayur	Ashoka	Zorawar
12:10	13:30	Track 4A: Intelligence on Silicon Session Chair: Dr. Manish Sharma, Samsung	Track 4B: Design Automation Session Chair: Prof. Susmita Sur-Kolay, ISI Kolkata	Track 4C: Embedded Systems – II Session Chair: Prof. Anshul Kumar, IIT Delhi	Industry Forum Talks 12:10 - 01:30 Next Gen AI Acceleration for Mobile Devices Sumit Goswami Qualcomm 12:35 - 13:00 ON Image sensors for Autonomous Driving Anirudh Oberoi ONSEMI 13:00 - 13:25 A High Performance DSP Architecture for Audio & Speech Processing and Neural Networks Ajay Homkar Cadence Design Systems	Women In Engineering (WiE) Forum Talk - The High Achievers Session Chair: Ashwini Khandekar Intel
						12:10 - 12:35 Lipika Dey TCS
		UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs Kala S, Babita Jose and Nalesh S Cochin University of Science and Technology Jimson Mathew, Indian Institute of Technology, Patna	RiverOpt: A Multiobjective Optimization Framework based on Modified River Formation Dynamics Heuristic Satyabrata Dash and Rudra Sankar Dhar National Institute of Technology Mizoram Sukanta Dey, Prof. Gaurav Trivedi and Anish J. Augustine Indian Institute of Technology Guwahati Jan Pidanič and Zdeněk Němec Fakulta elektrotechniky a informatiky, Katedra elektrotechniky, University of Pardubice	Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA Swagata Mandal, Sreetama Sarkar, Wong Ming Ming and Anupam Chattopadhyay Nanyang Technological University Amlan Chakrabarti, University of Calcutta
		The Ramifications of Making Deep Neural Networks Compact Nandan Kumar Jha, Sparsh Mittal and Govardhan Mattela Indian Institute of Technology Hyderabad	Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode-based Array Amartya Dutta, B. P. Poddar Institute of Management and Technology Riya Majumder, Supreme Knowledge Foundation Group of Institutions Debasis Dhal and Rajat Kumar Pal University of Calcutta	Multidimensional Grid Aware Address Prediction for GPGPU Shivani Tripathy, Debiprasanna Sahoo and Manoranjan Satpathy Indian Institute of Technology Bhubaneswar		12:35 - 13:00 Reena Dayal Yadav Microsoft
		Machine Learning based Power Efficient Approximate 4:2 Compressors for Imprecise Multipliers Ravindra JVR and Lavanya Maddisetty Vardhaman College of Engineering	Parasitic-Aware Automatic Analog CMOS Circuit Design Environment Subhash Patel, Kirtan Technologies Rajesh Thakker, VGEC, Ahmedabad	Efficient Heap Data Management on Software Managed Manycore Architectures Jing Lu, Jinn-Pean Lin and Aviral Shrivastava Arizona State University		13:00 - 13:25 Viji Ranganna QC
		MAVI: Mobility Assistant for Visually Impaired Using Deep Learning and Cloud Services	Ultra Low Power Low Frequency On-Chip Oscillator for Elapsed Time Counter	In situ Latency Monitoring for Heterogeneous Real-time Systems

		Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan and Chetan Arora Indraprastha Institute of Information Technology, Delhi	Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Sujata Kotabagi, Shraddha Hiremath, Dr. Saroja Siddamal and Dr. Nalini Iyer KLE Technological University	Martin Geier, Tobias Burghart, Martin Hackl and Samarjit Chakraborty Technical University of Munich
13:30	14:30	LUNCH
14:30	15:15	Keynote at Zorawar Auditorium Alok Jain Cadence Design Systems
		Panel Discussion at Zorawar Auditorium				Mayur
15:25	16:10	Women in Engineering - Be the change Moderator: Seema Naswa, Cadence Design Systems Panelists: Pamela Kumar, Director General, Telecommunications Standards Development Society of India Priya G., CEO, Radiant Global Solutions Shobha Vasudevan, Associate Professor, University of Illinois at Urbana Champaign Sumedha Limaye, Director of Engineering, Intel				Ph.D Forum: Thesis-B Session Chair: Hitesh Garg, NXP Semiconductor
16:10	16:30	Tea Break
16:30	17:50	Track 5A: IoT and CPS Session Chair: Dr. Kaushik Saha, Samsung	Track 5B: Analog / Mixed-Signal– II Session Chair: Prof. Qadeer Khan, IIT Madras	Track 5C: Digital Design – II Session Chair: Prof. Anupam Chattopadhyay, NTU, Singapore	Industry Forum C 16:30 - 17:05 Relevance of Intelligent ASIC solutions for Hardware optimization Rajiv Mittal Si2Chip 17:05 - 17:30 Deep Learning in Next generation edge devices Vijay Kodavalla Wipro	Panel Discussion : Hardware and Security – Opportunities & Risks Moderator: Amit Verma, Deputy Director – Data Security Council of India Panelists: Mr. Rajamohan Varambally, Director Technology – Research and Development, STMicroelectronics Mr. Amardeep Punhani, Senior Director - Digital IP, NXP Mr. Amit Sharma, Additional Director, DRDO, Government of India Mr. Sumit Goswami, Senior Director Of Engineering, Qualcomm
		Investigation of Unified emerging-NVM SoC Architecture for IoT-WSN Applications Vivek Parmar, Swatilekha Majumdar, Preeti Ranjan Panda and Manan Suri Indian Institute of Technology Delhi	A Mismatch Resilient 16-bit 20 MS/s Pipelined ADC Satyajit Mohapatra, Indian Institute of Technology, Gandhinagar, Gujarat Dr. Hari Shanker Gupta, Nihar Mohapatra, Sanjeev Mehta and Arup Roy Chowdhury Space Applications Centre Nisha Pandya, LD College of Engineering	High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio Rahul Shrestha, Pooja Bansal and Srikant Srinivasan Indian Institute of Technology Mandi
		A 75-μW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application Kundan Kumar, Raghunath K P, Akshay Muraleedharan and Gaurab Banerjee Indian Institute of Science Javed S Gaggatur, Terminus Circuits Pvt Ltd	Large dynamic range Readout Integrated Circuit for Infrared Detectors Dr. Hari Shanker Gupta, Sanjeev Mehta and Arup Roy Chowdhury Space Applications Centre Dinesh K Shrama and Maryam Shojaei Baghini Department of Electrical Engineering, Indian Institute of Technology, Bombay Powai, Mumbai A S Kiran Kumar, India Space Research Organization	VLSI Architectures for Jacobi Symbol Computation Ayan Palchaudhuri and Anindya Sundar Dhar Indian Institute of Technology Kharagpur
		Perturbation based Workload Augmentation for Comprehensive Functional Safety Analysis Prasanth V, Texas Instruments, Bangalore Rubin Parekhji, Texas Instruments (India) Pvt. Ltd. Bharadwaj Amrutur, Indian Institute of Science, Bangalore	Current DAC based -40dB PSRR Configurable Output LDO in BCD Technology Vivek Tyagi, Vikas Rana, Laura CAPECCHI, Marcella CARISSIMI, Riccardo ZURLA and Marco Pasotti ST Microelectronics	Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop Shubhanshu Gupta and Joycee Mekie Indian Institute of Technology Gandhinagar
		A Double Pumped Single-line-cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications Arijit Banerjee and Benton H. Calhoun University of Virginia	Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices Maneesh Pandey, Mohit Goyal and Parul Kumar Sharma NXP Semiconductors Rohit Sharma, Indian Institute of Technology Ropar	k-core: Hardware Accelerator for k-mer Generation and Counting used in computational genomics Simmi M Bose, S Saravanan and Madhura Purnaprajna Dept. CSE, Amrita School of Engineering Varsha S Lalapura, Dept. ECE, Amrita School of Engineering
17:50	18:15	Break
18:15	20:30	Awards and Cultural Program at Zorawar Auditorium
20:30	21:00	Banquet Talk at Zorawar Auditorium Title Enabling the Data Driven Economy Jaswinder Ahuja Cadence Design Systems
21:00	22:30	Dinner

		January 9, 2019 (Wednesday)
8:00	8:50	Registration
8:50	9:35	Keynote at Zorawar Auditorium Title : Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems Kaushik Roy Edward G. Tiedemann Jr. Distinguished Professor of Electrical and Computer Engineering, Purdue University
9:35	10:20	Keynote at Zorawar Auditorium
10:20	10:40	Tea/Coffee Break
		Taber	Shamsher	Ashoka	Mayur	Zorawar
10:40	12:00	Track 6A: Security – II Session Chair: Prof. Prathima Agrawal, Auburn University	Track 6B: Test and Validation - II Session Chair: Prof. Sandeep Chandran, IIT Palakkad	Track 6C: Emerging Tech – II Session Chair: Prof. Sukanta Bhattacharjee, New York University	Ph.D Forum -Poster - A Session Chair: Prof. Amit Patra, IIT Kharagpur	User Design Track A Session Chair: Namita Sharma, Intel
		Novel Randomized & biased Placement For FPGA Based Robust Random Number Generator with Enhanced Uniqueness Arjun Chauhan and Vineet Sahula Malaviya National Institute of Technology, Jaipur Atanendu Mandal, CEERI, Pilani	Improving Performance of Path Based Equivalence Checker using Counter-example Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri Indian Institute of Technology Guwahati	An Efficient Design Approach for Implementation of 2 bit Ternary Flash ADC Using Optimized Complementary TFET Devices Sanjay Vidhyadharan, Ramakant, A.Krishna Shyam, Mohit P Hirpara, Tanmay Chaudhary and Surya Shankar Dan, BITS Pilani, Hyderabad Campus Abhay SV, SRM Institute of Science and Technology, Chennai
		SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection Amr Sayed Ahmed, Syosil Aps Jawad Haj-Yahya, A*Star Anupam Chattopadhyay, Nanyang Technological University	Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays Manobendra Nath Mondal, Susmita SurKolay and Bhargab Bhattacharya Indian Statistical Institute, Kolkata	Optimizing Quantum Circuits for Modular Exponentiation Rakesh Das and Hafizur Rahaman Indian Institute of Engineering Science and Technology,Shibpur Anupam Chattopadhyay, Nanyang Technological University
		Linear Approximation and Differential Attacks on Logic Locking Techniques Ghanshyam Bairwa, Souvik Mandal, Tatavarthy Venkat Nikhil and Bodhisatwa Mazumdar Indian Institute of Technology Indore	A Methodology for SAT-based Electrical Error Debugging during Post-silicon Validation Binod Kumar and Virendra Singh Indian Institute of Technology Bombay Masahiro Fujita, University of Tokyo	A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices Piyali Datta, Arpan Chakraborty and Rajat Kumar Pal University of Calcutta
		Efficient Post-Silicon Validation of Network-on-Chip using Wireless Links Sidhartha Sankar Rout and Sujay Deb Indraprastha Institute of Information Technology Kanad Basu, NYU	Test Configuration Generation for different FPGA Architectures for Application Independent Testing Shukla Banik, Suchismita Roy and Bibhash Sen NIT Durgapur	Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked With Standard 45 nm CMOS Technology for Ternary Logic Applications Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit Hirpara, Tanmay Chaudhary and Surya Shankar Dan BITS Pilani, Hyderabad Campus
12:00	12:10	Break
12:10	13:30	Track 7A: Embedded Systems - III Session Chair: Prof. John Jose, IIT Guwahati	Track 7B: Digital Design – III Session Chair: Prof. Hafizur Rahaman, IIEST Shibpur	Track 7C: Power and Energy - II Session Chair: Arun Joseph, IBM		User Design Track B Session Chair: Atul Bhargava, ST Microelectronics
		Write Variation aware Cache Partitioning for improved lifetime in Non-Volatile Caches	Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems	Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis
		Arijit Nath and Hemangee Kapoor Indian Institute of Technology Guwahati	Jayaraj Kidav, Dr. Perumal M Pillai and Sreejeesh S G NIELIT Calicut Dr. N M Sivamangai, Karunya Institute of Technology and Sciences	Arun Joseph, Spandana Rachamalla, Shashidhar Reddy and Nagu Dhanwada IBM
		Applying Modified Householder Transform to Kalman Filter Farhad Merchant, Institute for Communication Technologies and Embedded Systems, RWTH Aachen University Tarun Vatwani and Anupam Chattopadhyay Nanyang Technological University Somyendu Raha and S K Nandy Indian Institute of Science Ranjani Narayan, Morphing Machines Pvt. Ltd Rainer Leupers, RWTH Aachen University	Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader Shankar Joshi, Rahul Pathak and Raghavendra Kongari NXP India	HEART: A Heterogeneous Energy-Aware Real-Time scheduler Sanjay Moulik, RAJESH DEVARAJ and Arnab Sarkar Indian Institute of Technology Guwahati
		Area efficient & High performance Word line Segmented architecture in 7nm FinFET SRAM compiler Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja and Amit Khanuja Synopsys (India) Pvt. Ltd.	Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad and Ravindra Shrivastava Synopsys (India) Pvt. Ltd.	Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic Panel Shubham Negi, Ashis Maity, Mrigank S H and Amit Patra Indian Institute of Technology Kharagpur
		Design of an optimized CMOS ELM accelerator Manoj Sharma, Umesh Lohani, Vivek Parmar and Manan Suri Indian Institute of Technology Delhi	Majority Logic: Prime Implicants and n-input Majority Term Equivalence Rajeswari Devadoss, Kolin Paul and M. Balakrishnan Indian Institute of Technology Delhi	Energy Efficient Power Distribution on Many-Core SoC Mustafa Shihab, University of Texas at Dallas Vishwani Agrawal, Auburn University
13:30	14:30	LUNCH
		Keynote at Zorawar Auditorium
14:30	15:15	Title : In Memory Compute - Technology Architecture Confluence Vijaykrishnan Narayanan Distinguished Professor of Engineering and Electrical Engineering and Computer Science, Pennsylvania State University
		Panel Discussion at Zorawar Auditorium				Mayur
15:25	16:10	Panel Discussion: Academia-Industry Collaboration: Challenges in the Research Pipeline Panelists: M. Balakrishnan, Deputy Director Strategy and Planning and Professor of Computer Science & Engg, IIT Delhi David Yeh, Senior Science Director, Semiconductor Research Corporation Sreenivas Subramoney, Intel India Design Centre Chandra Shekhar, CEERI, Pilani Aviral Shrivastava, Associate Professor, Arizona State University				Ph.D Forum -Poster - B
16:10	16:40	Tea Break
Interactive Presentation (IP) Poster Session [4:30 – 6:00 pm] Current Collapse reduction technique using N-doped buffer layer into the bulk region of a Gate Injection Transistor Koushik Bharadwaj,GUIST (Gauhati University) Ashok Ray, Assistant Professor, Dept. of ECE, NERIST, Nirjuli Sushanta Bordoloi, Dept. of ECE, National Institute of Technology Mizoram Prof. Gaurav Trivedi, EEE Department, IIT Guwahati
Design and analysis of a minimally invasive and ECG controlled Ventricular Assistive Device Prajwal Sharma, Prashanthi K, Vinay Chandrashekar, Krishna Nagaraja, Vikas Vazhiyal and Madhav Rao Indraprastha Institute of Information Technology, Bangalore
A simple Synthesis Process for Combinational QCA Circuits: QSynthesizer Vaishali Dhare and Usha Mehta Institute of Technology, Nirma University
Mapping of Boolean Logic Functions onto 3D Memristor Crossbar Naveen Murali G., P. Satya Vardhan, F Lalchhandama and Indranil Sengupta Indian Institute of Technology Kharagpur Kamalika Datta, National Institute of Technology Meghalaya
Stability Analysis of SRAM designed using In$_{0.53}$Ga$_{0.47}$As nFinFET with underlap region JAY PATHAK and Anand Darji SVNIT, Surat
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications Dinesh Rajasekharan, Indian Institute of Technology Kanpur Amit Ranjan Trivedi, University of Illinois at Chicago Yogesh Chauhan, Indian Institute of Technology Kanpur
Reconfigurable Digital Logic Gate based on Neuromorphic Approach Navin Singhal, M Santosh and S.C. Bose CSIR-CEERI Pilani
Realizing Boolean functions using Probabilistic Spin Logic (PSL) Vaibhav Agarwal and Sneh Saurabh Indraprastha Institute of Information Technology, Delhi
Comparative Study of Analog Matching Structures in 28FDSOI VARUN KUMAR DWIVEDI, Madhvi Sharma and Manoj Kumar Sharma Stmicroelectronics Pvt Ltd Meenakshi Didharia, Texas Instruments
A Model of Spurs for ΔΣ Fractional PLLs Debdut Biswas and Tarun Kanti Bhattacharyya
Exploiting Negative Control Lines and Nearest neighbor for Improved Comparator Design Tathagato Bose, IBM Kamalika Datta, National Institute of Technology Meghalaya Indranil Sengupta, Indian Institute of Technology Kharagpur
Intelligent Scheduling of Smart Appliances in Energy Efficient Buildings: A Practical Approach Nilotpal Chakraborty, Arijit Mondal and Samrat Mondal Indian Institute of Technology Patna
Design and Implementation of Threshold Logic Functions using Memristors Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Indrajit Chakrabarti and Indranil Sengupta Indian Institute of Technology, Kharagpur Kamalika Datta, National Institute of Technology Meghalaya
A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI Robustness Sana Mujeeb and Krishna Kanth Gowri Avalur AMS Semiconductors India Pvt. Ltd
On chip RF to DC power converter for biomedical applications Harshal Chapade and Rajesh Zele Indian Institute of Technology Bombay
Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination Karthik Narayanan, Vinayak Honkote and Dibyendu Ghosh Intel Corporation Swamy Baldev, NIT, Meghalaya
Multi-Application based Network-on-Chip Design for Mesh-of-Tree topology using Global Mapping and Reconfigurable Architecture Monil Shah, Mohit Upadhyay, Veda Bhanu and Soumya J Birla Institute of Technology and Science - Pilani, Hyderabad campus
Extending STL basic operators used in 3GPP codecs to leverage features of modern DSP architectures Ajay Homkar, Satish Patil, Lukman Rahumathulla, Raj Pawate and Sachin Ghanekar Cadence Design Systems, Pune
A Machine Learning Based Approach to Predict Power Efficiency of S-boxes Rajat Sadhukhan, Nilanjan Datta and Debdeep Mukhopadhyay Indian Institute of Technology Kharagpur
RF and RFID based Object Identification and Navigation system for the Visually Impaired Gaurav Mishra, Urvi Ahluwalia, Karan Praharaj and Shreyangi Prasad Shiv Nadar University
Design and Implementation of Low-power High-throughput PRNGs for Security Applications Bikram Paul,Sushree Sila P. Goswami, Sunil Dutt and Gaurav Trivedi Indian Institute of Technology Guwahati Apratim Khobragade and Javvaji Soumith National Institute of Technology Tiruchirapalli
Hardware Trojan Detection by Stimulating Transitions in Rare Nets Tapobrata Dhar, Surajit Kumar Roy and Chandan Giri Department of IT, IIEST, Shibpur
An Enhanced Artificial Bee Colony Algorithm and Automatic Analog CMOS Circuit Design Subhash Patel, Kirtan Technologies Rajesh Thakker, VGEC, Ahmedabad
Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric Authentication Timothy Dee, Ian Richardson and Akhilesh Tyagi Lowa State University
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process Hitesh Shrimali, Ashish Joshi and Indu Yadav Indian Institute of Technology Mandi Ettore Ruscino, Università degli Studi di Genova Valentino Liberali, and Attilio Andreazza Università degli Studi di Milano
WCET-Aware Stack Frame Management of Embedded Systems using Scratchpad Memories Yooseong Kim, Synopsys Mohammad Khayatian and Aviral Shrivastava Arizona State University
Self-Organizing Maps-based Flexible and High-Speed Packet Classification in Software Defined Networking Shih-Chang Hung, Michigan State University Nick Iliev, Balajee Vamanan and Amit Ranjan Trivedi University of Illinois at Chicago
A 0.8V VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology using Repeated-Pulse Wordline Suppression Scheme Ashish Kumar, ST Microelectronics Pvt Ltd Mohammad Aftab Alam, Zia Semiconductor Pvt Ltd Gangaikondam Visweswaran, IIIT Delhi
Tea and Wrap Up

Main Conference Technical Programme - Detailed

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